Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
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PMIC5000/PMIC5010 Power Management IC Standard |
JESD301-1A.03 | Feb 2025 |
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor update to correct the document name, and also remove the extraneous hard return in the middle of the description between “as” and “used”. Committee(s): JC-40.1 Free download. Registration or login required. |
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Automotive Solid State Drive (SSD) Device StandardRelease Number: 1.1 |
JESD312 | Jan 2025 |
This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features for a solid state drive (SSD) targeted primarily at automotive applications. Free download. Registration or login required. |
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Universal Flash Storage (UFS)Release Number: Version 4.1 |
JESD220G | Dec 2024 |
This document replaces all prior versions; however, JESD220F August 2022 (version 4.0) remains available for reference purposes. This standard defines a UFS Universal Flash Storage electrical interface and a UFS memory device. Available for purchase: $423.00 Add to Cart Paying JEDEC Members may login for free access. |
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Universal Flash Storage Host Controller Interface (UFSHCI)Release Number: Version 4.1 |
JESD223F | Dec 2024 |
This document replaces all prior versions; however, JESD223E August 2022 (version 4.0) remains available for reference purposes. This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY]. Clause 4 provides a brief overview of the architectural overview of UFS. Clause 5 describes the register interface of UFSHCI. Clause 6 describes the data structure used by UFSHCI. Clause 7 provides a theory of operation for UFSHCI. Clause 8 describes the error recovery process for UFSHCI. Available for purchase: $220.00 Add to Cart Paying JEDEC Members may login for free access. |
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DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C AnnexRelease Number: Version 1.00 |
JESD323-A0-RCC | Dec 2024 |
This standard, “JESD323-A0-RCC, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C Annex” defines the design detail of x16, 1 Package Ranks DDR5 Clocked UDIMM. Free download. Registration or login required. |
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DDR5 DIMM Labels |
JESD401-5C | Nov 2024 |
This standard defines the labels that shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently. Committee(s): JC-45 Free download. Registration or login required. |
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Compression Attached Memory Module (CAMM2) Common Standard |
JESD318A Ver. 1.10 | Nov 2024 |
This standard defines the electrical and mechanical requirements for Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (DDR5 SDRAM CAMM2s) and Low Power Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (LP5 SDRAM CAMM2s). Committee(s): JC-45 Free download. Registration or login required. |
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LPDDR5/5X Compression Attached Memory Module (CAMM2) Raw Card E AnnexRelease Number: Version 1.00 |
JESD318-F0-RCE | Nov 2024 |
This standard, JESD318-F0-RCE, “LPDDR5/5X Compression Attached Memory Module (CAMM2) Raw Card E Annex”, defines the design detail of eight x16 subchannels from four 315-ball dual channel LPDDR5/5x devices. Committee(s): JC-45 Free download. Registration or login required. |
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DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A AnnexRelease Number: Version 1.00 |
JESD323-A0-RCA | Nov 2024 |
This standard, JESD323-A0-RCA, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A Annex” defines the design detail of x8, 1 Package Rank DDR5 NECC CUDIMM with Clock Driver. |
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DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A AnnexRelease Number: Version 1.00 |
JESD323-A0-RCA | Nov 2024 |
This standard, JESD323-A0-RCA, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A Annex” defines the design detail of x8, 1 Package Rank DDR5 NECC CUDIMM with Clock Driver. Free download. Registration or login required. |
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DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECCRelease Number: Version 1.00 |
JESD323-B4-RCD | Nov 2024 |
This standard, JESD323-B4-RCD, “DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 CUDIMM) Raw Card D Annex” defines the design detail of x8, 1 Package Rank DDR5 ECC CUDIMM with Clock Driver. Free download. Registration or login required. |
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DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card A AnnexRelease Number: Version 1.00 |
JESD324-V0-RCA | Nov 2024 |
This standard, JESD324-V0-RCA, “DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card A Annex” defines the design detail of x8, 1 Package Ranks DDR5 CSODIMM with Clock Driver. Free download. Registration or login required. |
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Descriptive Designation System for Electronic-device Packages and Footprints |
JESD30N | Nov 2024 |
This standard establishes requirements for the generation of electronic-device package designators for JEDEC. Free download. Registration or login required. |
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DDR5 Clocked Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 CSODIMM) Raw Card D AnnexRelease Number: Version 1.00 |
JESD324-W4-RCD | Nov 2024 |
This standard, JESD324-W4-RCD, “DDR5 Clocked Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 CSODIMM) Raw Card D Annex” defines the design detail of x8, 1 Package Ranks DDR5 CSODIMM with Clock Driver. Committee(s): JC-45.3 Free download. Registration or login required. |
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Serial Flash Discoverable Parameters (SFDP) |
JESD216G | Nov 2024 |
The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data. Committee(s): JC-42.4 Free download. Registration or login required. |
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DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card C AnnexRelease Number: Version 1.00 |
JESD324-V0-RCC | Nov 2024 |
This standard, JESD324-V0-RCC, "DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) RawCard C Annex" defines the design detail of x16, 1 Package Ranks DDR5 CSODIMM with Clock Driver. Committee(s): JC-45.3 Free download. Registration or login required. |
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LPDDR5/5X Serial Presence Detect (SPD) ContentsRelease Number: 1.0 |
JESD406-5A | Nov 2024 |
This publication describes the serial presence detect (SPD) values for all LPDDR5/5X memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. The storage capacity of the SPD non-volatile memory is limited, so a number of techniques are employed to optimize the use of these bytes, including overlays and run length limited coding. Committee(s): JC-45 Free download. Registration or login required. |
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Low Power Double Data Rate Interface for Non-Volatile Memory (LPDDR4X-NVM) Standard |
JESD326-4 | Nov 2024 |
This standard defines the Low Power Double Data Rate interface for Non-Volatile Memory (LPDDR4XNVM) Standard. This standard describes features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit single channel LPDDR4X-NVM device. LPDDR4X-NVM density ranges from 128Mb through 32Gb. Free download. Registration or login required. |
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NAND Flash Interface Interoperability |
JESD230G | Oct 2024 |
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Free download. Registration or login required. |
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Graphics Double Data Rate 7 SGRAM Standard (GDDR7) |
JESD239A | Sep 2024 |
This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.
Free download. Registration or login required. |