Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
Date![]() |
---|---|---|
ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITS: |
JESD8-2 | Mar 1993 |
This Addendum No. 2 to JEDEC Standard No. 8 provides standard operating voltage and interface levels that can be used by designers and application engineers as they develop and introduce new products. Covers the ECL logic family designated 300K ECL. The 300K ECL family is Voltage and Temperature Compensated, with I/O interface levels compatible with the existing 100K ECL and 101K ECl families. Committee(s): JC-16 Free download. Registration or login required. |
||
CERAMIC PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES - SUPERSEDED BY JESD9B, May 2011.Status: Rescinded, May 2011 |
JESD27 | Aug 1993 |
The intent of this standard is to be a guide in the manufacture and procurement of ceramic packages, especially for the hybrid industry. Manufacturers or ceramic packages and procuring activities for these packages will now be able to use this document as the means for agreement in the imposition of minimum requirements in qualification, screening, and quality conformance. Free download. Registration or login required. |
||
ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS: |
JESD12-1B | Aug 1993 |
The purpose of this standard is to promote the uniform use of abbreviations, terms, and definitions throughout the semiconductor industry. It is a useful guide for users, manufactures, educators, technical writers, and others interested in the characterization, nomenclature, and classification of semicustom integrated circuits. Committee(s): JC-44 Free download. Registration or login required. |
||
ADDENDUM No. 4 to JESD8 - CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS: |
JESD8-4 | Nov 1993 |
This Addendum No. 4 to JEDEC Standard No. 8 defines the dc input and output specifications for a low-level, high-speed interface for integrated devices that can be a super-set of LVCMOS and LVTTL. Committee(s): JC-16 Free download. Registration or login required. |
||
REQUIREMENTS FOR HANDLING ELECTROSTATIC-DISCHARGE-SENSITIVE (ESDS) DEVICES - SUPERSEDED BY EIA-625, November 1994.Status: Superseded |
JESD42 | Mar 1994 |
Committee(s): JC-13 Free download. Registration or login required. |
||
STANDARD DATA TRANSFER FORMAT BETWEEN DATA PREPARATION SYSTEM AND PROGRAMMABLE LOGIC DEVICE PROGRAMMER: |
JESD3-C | Jun 1994 |
This standard was developed to prevent the proliferation of data transfer formats that occurred with microprocessor development systems. The focus of the standard is on field programmable devices and their support tools. It is not intended for other types of semicustom logic devices or other types of fabrication or testing equipment. Committee(s): JC-42.1 Free download. Registration or login required. |
||
ADDENDUM No. 1 to JESD8: INTERFACE STANDARD FOR LOW VOLTAGE TTL-COMPATIBLE (LVTTL) VLSI DIGITAL CIRCUITSStatus: Incorporatedinto JESD8-A, June 1994. JESD8-A was replaced by JESD8-B, September 1999. |
JESD8-1 | Jun 1994 |
Committee(s): JC-16 Free download. Registration or login required. |
||
INTERFACE STANDARD FOR NOMINAL 0.3 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITSStatus: Incorporatedinto JESD8-A, June 1994. JESD8-A was replaced by JESD8-B, September 1999. |
JESD8-1A | Jun 1994 |
Committee(s): JC-16 Free download. Registration or login required. |
||
PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS - SUPERSEDED BY EIA-623, July 1994Status: Superseded |
JESD40 | Jul 1994 |
Committee(s): JC-13 Free download. Registration or login required. |
||
ADDENDUM No. 10 to JESD24 - TEST METHOD FOR MEASUREMENT OF REVERSE RECOVERY TIME trr FOR POWER MOSFET DRAIN-SOURCE DIODES:Status: ReaffirmedOctober 2002 |
JESD24-10 | Aug 1994 |
Test method to measure the reverse recovery characteristics of the drain source diode of a power MOSFET. Committee(s): JC-25 Free download. Registration or login required. |
||
MEASUREMENT METHOD FOR THERMAL RESISTANCE OF BRIDGE RECTIFIER ASSEMBLIES: RESCINDED, June 2002. Replaced by JESD282-B.Status: RescindedJune 2002 |
JESD45 | Dec 1994 |
Committee(s): JC-22.2 Free download. Registration or login required. |
||
REVERSE RECOVERY CHARACTERISTICS OF SILICON DIODES: RESCINDED June 2002.Status: Rescinded |
JESD41 | May 1995 |
Committee(s): JC-22.1 Free download. Registration or login required. |
||
ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS: |
JESD8-6 | Aug 1995 |
This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz. Committee(s): JC-16 Free download. Registration or login required. |
||
ADDENDUM No. 1 to JESD35, GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICSStatus: Rescinded |
JESD35-1 | Sep 1995 |
JESD35-1 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests. Committee(s): JC-14.2 |
||
MOISTURE-INDUCED STRESS SENSITIVITY FOR PLASTIC SURFACE MOUNT DEVICES - SUPERSEDED BY J-STD-020A, April 1999.Status: Rescinded, May 2000 |
JESD22-A112-A | Nov 1995 |
J-STD-020 is now on revision F. Free download. Registration or login required. |
||
STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES: |
JESD52 | Nov 1995 |
This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike. Committee(s): JC-40 Free download. Registration or login required. |
||
STANDARD FOR FAILURE ANALYSIS REPORT FORMAT:Status: Rescinded January 2025 |
JESD38 | Dec 1995 |
This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional objectives are to ensure that reports can be easily ready by users, satisfactorily reproduced on copying machines, adequately transmitted by telefax, and conveniently stored in standard filing cabinets. Committee(s): JC-14.4 Free download. Registration or login required. |
||
METHODOLOGY FOR THE THERMAL MEASUREMENT OF COMPONENT PACKAGES (SINGLE SEMICONDUCTOR DEVICE) |
JESD51 | Dec 1995 |
This standard and its subsequent addendum's, provides a standard for thermal measurement that, if followed fully, will provide correct and meaningful data that will allow for determination of junction temperature for specific conditions. The data can be used for package design evaluation, device characterization and reliability predictions. Free download. Registration or login required. |
||
INTEGRATED CIRCUIT THERMAL MEASUREMENT METHOD - ELECTRICAL TEST METHOD (SINGLE SEMICONDUCTOR DEVICE): |
JESD51- 1 | Dec 1995 |
The purpose of this test method is to define a standard Electrical Test Method (ETM) that can be used to determine the thermal characteristics of single integrated circuit devices housed in some form of electrical package. This method will provide a basis for comparison of different devices housed in the same electronic package or similar devices housed in different electronic packages. Committee(s): JC-15.1 Free download. Registration or login required. |
||
MANAGEMENT OF COMPONENT OBSOLESCENCE BY GOVERNMENT CONTRACTORS: RESCINDED, October 2002Status: RescindedOctober 2002 |
JESD53 | Jan 1996 |
Free download. Registration or login required. |