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Title	Document #	Date
DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard Release Number: Version 1.1	JESD309A	Feb 2025
This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM SODIMMs). These DDR5 SODIMMs are intended for use as main memory when installed in Computers, laptops and other systems. Committee(s): JC-45, JC-45.3 Free download. Registration or login required.
Graphics Double Data Rate 7 SGRAM Standard (GDDR7)	JESD239B	Feb 2025
This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. Committee(s): JC-42, JC-42.1 Free download. Registration or login required.
PMIC5120 Power Management IC Standard Release Number: Version 1.0	JESD301-6	Feb 2025
This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5120 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5120 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Unless otherwise noted in the document, any illegal operation is not allowed and device operation is not guaranteed. Committee(s): JC-40, JC-40.1 Free download. Registration or login required.
Descriptive Designation System for Electronic-device Packages and Footprints	JESD30O	Feb 2025
This standard establishes requirements for the generation of electronic-device package designators for JEDEC. Committee(s): JC-11, JC-11.2 Free download. Registration or login required.
PMIC5000/PMIC5010 Power Management IC Standard	JESD301-1A.03	Feb 2025
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor update to correct the document name, and also remove the extraneous hard return in the middle of the description between “as” and “used”. Committee(s): JC-40.1 Free download. Registration or login required.
DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card E Annex Release Number: Version 2.00	JESD305-R8-RCE	Feb 2025
This standard, JESD305-R8-RCE, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card E Annex, defines the design detail of x8, 2 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard. Committee(s): JC-45, JC-45.1 Free download. Registration or login required.
Automotive Solid State Drive (SSD) Device Standard Release Number: 1.1	JESD312	Jan 2025
This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features for a solid state drive (SSD) targeted primarily at automotive applications. Committee(s): JC-64, JC-64.8 Free download. Registration or login required.
Universal Flash Storage (UFS) Release Number: Version 4.1	JESD220G	Dec 2024
This document replaces all prior versions; however, JESD220F August 2022 (version 4.0) remains available for reference purposes. This standard defines a UFS Universal Flash Storage electrical interface and a UFS memory device. Committee(s): JC-64, JC-64.1 Available for purchase: $423.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
Universal Flash Storage Host Controller Interface (UFSHCI) Release Number: Version 4.1	JESD223F	Dec 2024
This document replaces all prior versions; however, JESD223E August 2022 (version 4.0) remains available for reference purposes. This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY]. Clause 4 provides a brief overview of the architectural overview of UFS. Clause 5 describes the register interface of UFSHCI. Clause 6 describes the data structure used by UFSHCI. Clause 7 provides a theory of operation for UFSHCI. Clause 8 describes the error recovery process for UFSHCI. Committee(s): JC-64, JC-64.1 Available for purchase: $220.00 Add to Cart Paying JEDEC Members may login for free access.
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C Annex Release Number: Version 1.00	JESD323-A0-RCC	Dec 2024
This standard, “JESD323-A0-RCC, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C Annex” defines the design detail of x16, 1 Package Ranks DDR5 Clocked UDIMM. Committee(s): JC-45, JC-45.3 Free download. Registration or login required.

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JEDEC Education Series: Memory, Mobile & Modules