Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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Power Cycling |
JESD22-A122B | Nov 2023 |
This Test Method establishes a uniform method for performing solid state device package power cycling stress test. Free download. Registration or login required. |
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POWER AND TEMPERATURE CYCLING |
JESD22-A105D | Jan 2020 |
The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes and simultaneously the operating biases are periodically applied and removed. It is intended to simulate worst case conditions encountered in application environments. The power and temperature cycling test is considered destructive and is only intended for device qualification. This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures. Free download. Registration or login required. |
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PHYSICAL DIMENSION:Status: ReaffirmedJune 2006, January 2016, September 2021 |
JESD22-B100B | Jun 2003 |
The standard provides a method for determining whether the external physical dimensions of the device are in accordance with the applicable procurement document. This revision includes a change in details to be specified by the procurement document. Committee(s): JC-14.1 Free download. Registration or login required. |
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Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature |
JESD22-B112C | Nov 2023 |
This test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of thermal conditions experienced during the surface-mount soldering operation. Free download. Registration or login required. |
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OUTLIER IDENTIFICATION AND MANAGEMENT SYSTEM FOR ELECTRONIC COMPONENTS, RESCINDED January 2009. Replaced by JESD50.Status: RescindedJanuary 2009 |
JESD62-A | May 2002 |
Relevant JESD62 content has been consolidated into JESD50B, published October 2008 -Special Requirments for Maverick Product Elimination-. Committee(s): JC-14.3 Free download. Registration or login required. |
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MOISTURE-INDUCED STRESS SENSITIVITY FOR PLASTIC SURFACE MOUNT DEVICES - SUPERSEDED BY J-STD-020A, April 1999.Status: Rescinded, May 2000 |
JESD22-A112-A | Nov 1995 |
J-STD-020 is now on revision F. Free download. Registration or login required. |
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METHODS FOR CALCULATING FAILURE RATES IN UNITS OF FITS |
JESD85A | Jul 2021 |
This standard establishes methods for calculating failure rates in units of FITs by using data in varying degrees of detail such that results can be obtained from almost any data set. The objective is to provide a reference to the way failure rates are calculated. Committee(s): JC-14.3 Free download. Registration or login required. |
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METHOD FOR DEVELOPING ACCELERATION MODELS FOR ELECTRONIC DEVICE FAILURE MECHANISMS |
JESD91B | Mar 2022 |
The method described in this document applies to all reliability mechanisms associated with electronic devices. The purpose of this standard is to provide a reference for developing acceleration models for defect-related and wear-out mechanisms in electronic devices. Committee(s): JC-14.3 Free download. Registration or login required. |
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METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESSStatus: Reaffirmed September 2018 |
JESD202 | Mar 2006 |
This is an accelerated stress test method for determining sample estimates and their confidence limits of the median-time-to-failure, sigma, and early percentile of a log-Normal distribution, which are used to characterize the electromigration failure-time distribution of equivalent metal lines subjected to a constant current-density and temperature stress. Failure is defined as some pre-selected fractional increase in the resistance of the line under test. Analysis procedures are provided to analyze complete and singly, right-censored failure-time data. Sample calculations for complete and right-censored data are provided in Annex A. The analyses are not intended for the case when the failure distribution cannot be characterized by a single log-Normal distribution. Free download. Registration or login required. |
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MECHANICAL SHOCK – DEVICE AND SUBASSEMBLY |
JESD22-B110B.01 | Jun 2019 |
Device and Subassembly Mechanical Shock Test Method is intended to evaluate devices in the free state and assembled to printed wiring boards for use in electrical equipment. The method is intended to determine the compatibility of devices and subassemblies to withstand moderately severe shocks. The use of subassemblies is a means to test devices in usage conditions as assembled to printed wiring boards. Mechanical Shock due to suddenly applied forces, or abrupt change in motion produced by handling, transportation or field operation may disturb operating characteristics, particularly if the shock pulses are repetitive. This is a destructive test intended for device qualification.This document also replaces JESD22-B104. Free download. Registration or login required. |
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MECHANICAL SHOCKStatus: Supersededby JEDEC JESD22-B110B, July 2013 |
JESD22-B104C | Nov 2004 |
This test is intended to determine the suitability of component parts for use in electronic equipment that may be subjected to moderately severe shocks as a result of suddenly applied forces or abrupt changes in motion produced by rough handling, transportation, or field operation. Shock of this type may disturb operating characteristics, particularly if the shock pulses are repetitive. This is a destructive test intended for device qualification. It is normally applicable to cavity-type packages. |
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MECHANICAL COMPRESSIVE STATIC STRESS TEST METHOD |
JESD22-B119 | Oct 2018 |
This test method is intended for customers to determine the ability of a device to withstand the mechanical compressive static stress generated when a heat sink is being initially attached to the device, and to help the customer generate design rules for their heat sink design and validate their thermal solution. This test method does not assess the long-term effects of static stress. Committee(s): JC-14.1 Free download. Registration or login required. |
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MEASURING WHISKER GROWTH ON TIN AND TIN ALLOY SURFACE FINISHESStatus: Reaffirmed May 2014, September 2019 |
JESD22-A121A | Jul 2008 |
The predominant terminal finishes on electronic components have been Sn-Pb alloys. As the industry moves toward Pb-free components and assembly processes, the predominant terminal finish materials will be pure Sn and alloys of Sn, including Sn-Bi and Sn-Ag Pure Sn and Sn-based alloy electrodeposits and solder-dipped finishes may grow tin whiskers, which could electrically short across component terminals or break off the component and degrade the performance of electrical or mechanical parts. Free download. Registration or login required. |
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MARKING, SYMBOLS, AND LABELS FOR IDENTIFICATION OF LEAD (Pb) FREE ASSEMBLIES, COMPONENTS, AND DEVICES - SUPERSEDED BY J-STD-609, August 2007Status: Supersededby J-STD-609, August 2007 |
JESD97 | May 2004 |
Committee(s): JC-14.1, JC-14.4 Free download. Registration or login required. |
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MARKING PERMANENCYStatus: Reaffirmed August 2024 |
JESD22-B107D | Mar 2011 |
This test method provides two tests for determining the marking permanency of ink marked integrated circuits. A new non-destructive tape test method is introduced to quickly determine marking integrity. The test method also specifies a resistance to solvents method based upon MIL Std 883 Method 2015. Free download. Registration or login required. |
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MARK LEGIBILITY |
JESD22-B114B | Jan 2020 |
This standard describes a nondestructive test to assess solid state device mark legibility. The specification applies only to solid state devices that contain markings, regardless of the marking method. It does not define what devices must be marked or the method in which the device is marked, i.e., ink, laser, etc. The standard is limited in scope to the legibility requirements of solid state devices, and does not replace related reference documents listed in this standard. Committee(s): JC-14.1 Free download. Registration or login required. |
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LOW TEMPERATURE STORAGE LIFEStatus: Reaffirmed May 2021 |
JESD22-A119A | Oct 2015 |
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices Low Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). During the test reduced temperatures (test conditions) are used without electrical stress applied. This test may be destructive, depending on Time, Temperature and Packaging (if any). Committee(s): JC-14.1 Free download. Registration or login required. |
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LEAD INTEGRITYStatus: Reaffirmed - May 2023 |
JESD22-B105E | Feb 2017 |
This test method provides various tests for determining the integrity lead/package interface and the lead itself when the lead(s) are bent due to faulty board assembly followed by rework of the part for reassembly. For hermetic packages it is recommend that this test be followed by hermeticity tests in accordance with Test Method A109 to determine if there are any adverse effects from the stresses applied to the seals as well as to the leads. These tests, including each of its test conditions, is considered destructive and is only recommended for qualification testing. This test is applicable to all through-hole devices and surface-mount devices requiring lead forming by the user. Free download. Registration or login required. |
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ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE:Status: Reaffirmed September 2018 |
JESD61A.01 | Oct 2007 |
This standard describes an algorithm for the execution of the isothermal test, using computer-controlled instrumentation. The primary use of this test is for the monitoring of microelectronic metallization lines at wafer level (1) in process development, to evaluate process options, (2) in manufacturing, to monitor metallization reliability and (3) to monitor/evaluate process equipment. While it is developed as a fast WLR test, it can also be an effective tool for complementing the reliability data obtained through the standard package level electromigration test. Free download. Registration or login required. |
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Information Requirements for the Qualification of Solid State Devices |
JESD69D | Jun 2024 |
This standard defines the requirements for the device qualification package, which the supplier provides to the customer. Free download. Registration or login required. |