Global Standards for the Microelectronics Industry
Standards & Documents Search
Title![]() |
Document # | Date |
---|---|---|
STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:Status: Reaffirmed 4/17/23 |
JESD63 | Apr 2023 |
This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process. Committee(s): JC-14.2 Free download. Registration or login required. |
||
STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD: |
JESD37A | Aug 2017 |
This standard details techniques for estimating the values of a two parameter lognormal distribution from complete lifetime data (all samples in an experiment have failed) or singly right-censored lifetime data (the experiment have failed) or singly right-censored lifetime data gathered from rapid stress test; however, not all types of failure data can be analyzed with these techniques. Committee(s): JC-14.2 Free download. Registration or login required. |
||
STANDARD FOR FAILURE ANALYSIS REPORT FORMAT:Status: Rescinded January 2025 |
JESD38 | Dec 1995 |
This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional objectives are to ensure that reports can be easily ready by users, satisfactorily reproduced on copying machines, adequately transmitted by telefax, and conveniently stored in standard filing cabinets. Committee(s): JC-14.4 Free download. Registration or login required. |
||
SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENTStatus: Reaffirmed |
JESD50C | Jan 2018 |
This standard applies to the identification and control of Maverick Product that can occur during fabrication, assembly, packaging, or test of any electronic component. It can be implemented for an entire product line or to segregate product that has a higher probability of adversely impacting quality or reliability. Free download. Registration or login required. |
||
SOLDERABILITYStatus: Rescinded 2014, this document has been replaced by J-STD-002D. |
JESD22-B102E | Oct 2007 |
This test method provides optional conditions for preconditioning and soldering for the purpose of assessing the solderability of device package terminations. It provides procedures for dip & look solderability testing of through hole, axial and surface mount devices and a surface mount process simulation test for surface mount packages. The purpose of this test method is to provide a means of determining the solderability of device package terminations that are intended to be joined to another surface using lead (Pb) containing or Pb-free solder for the attachment. Committee(s): JC-14.1 |
||
SOLDER BALL SHEARStatus: Reaffirmed September 2020 |
JESD22-B117B | May 2014 |
The purpose of this test is conducted to assess the ability of solder balls to withstand mechanical shear forces that may be applied during device manufacturing, handling, test, shipment and end-use conditions. Solder ball shear is a destructive test. Free download. Registration or login required. |
||
SOLDER BALL PULLStatus: Reaffirmed September 2021 |
JESD22-B115A.01 | Jul 2016 |
This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. This is a minor editorial revision to JESD22-A115A. Free download. Registration or login required. |
||
SEMICONDUCTOR WAFER AND DIE BACKSIDE EXTERNAL VISUAL INSPECTION |
JESD22-B118A | Nov 2021 |
This inspection method is for product semiconductor wafers and dice prior to assembly. This test method defines the requirements to execute a standardized external visual inspection and is a non-invasive and nondestructive examination that can be used for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required. |
||
SALT ATMOSPHEREStatus: Reaffirmed September 2020 |
JESD22-A107C | Apr 2013 |
Salt atmosphere is a destructive, accelerated stress that simulates the effects of severe seacoast atmosphere on all exposed surfaces. Such stressing and post-stress testing determine the resistance of solid-state devices to corrosion and may be performed on commercial and industrial product in molded or hermetic packages. Free download. Registration or login required. |
||
RF BIASED LIFE (RFBL) TESTStatus: Reaffirmed October 2024 |
JESD226 | Jan 2013 |
This stress method is used to determine the effects of RF bias conditions and temperature on Power Amplifier Modules (PAMs) over time. These conditions are intended to simulate the devices’ operating condition in an accelerated way, and they are expected to be applied primarily for device qualification and reliability monitoring. The purpose of this test is for use to determine the effects of nominal DC and RF bias conditions and high temperature on Power Amplifier Modules (PAMs) over time. It simulates the devices’ operating condition in an accelerated way, and is primarily intended for device qualification testing and reliability monitoring which stresses all of the modules’ thermal and electrical failure mechanisms anticipated in typical use. Committee(s): JC-14.7 Free download. Registration or login required. |
||
RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICESStatus: Reaffirmed February 2023 |
JESD22-B106E | Nov 2016 |
This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. Committee(s): JC-14.1 Free download. Registration or login required. |
||
Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices |
JESD625C.01 | Mar 2024 |
This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM). Free download. Registration or login required. |
||
RELIABILITY QUALIFICATION OF POWER AMPLIFIER MODULESStatus: Reaffirmed October 2024 |
JESD237 | Mar 2014 |
This standard is intended to identify a core set of qualification tests that apply specifically for Power Amplifier Modules and their primary application in mobile devices such as cellular phones. This standard is intended to describe specific stresses and failure mechanisms that are specific to compound semiconductors and power amplifier modules. It is intended to establish more meaningful and efficient qualification testing. Committee(s): JC-14.7 Free download. Registration or login required. |
||
QUALITY SYSTEM ASSESSMENT - SUPERSEDED BY ANSI/EIA-670, June 1997.Status: Superseded |
JESD39-A | Jun 1997 |
Committee(s): JC-14.4 Free download. Registration or login required. |
||
QUALITY SYSTEM ASSESSMENT (SUPERSEDES EIA670): |
JESD670A | Oct 2013 |
This standard provides a checklist that is intended as a tool to allow users to assess the level of compliance of a quality management system to the requirements ISO 9001:2008. The questions in this checklist are of a generic nature and intended to be applicable to all organizations, not just those involved in the electronics industry. It can be useful while performing self-assessments of the organization or other internal audit procedures. It is not intended for use by a contracted third party registrar during a formal audit to the requirements of ISO 9001:2008. Committee(s): JC-14.4 |
||
PRODUCT DISCONTINUANCEStatus: Supersededby J-STD-048, November 2014 |
JESD48C | Dec 2011 |
This standard establishes the requirements for timely customer notification of planned product discontinuance, which will assist customers in managing end-of-life supply, or to transition on-going requirements to alternate products. |
||
PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS:Status: Rescinded |
JESD35A | Apr 2001 |
JESD35A was rescinded by the committee in June 2024 and has been superseded by JESD263. The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown. Committee(s): JC-14.2 |
||
PROCEDURE FOR WAFER-LEVEL DC CHARACTERIZATION OF BIAS TEMPERATURE INSTABILITIESStatus: Reaffirmed September 2021 |
JESD241 | Dec 2015 |
This Bias Temperature Instability (BTI) stress/test procedure is proposed to provide a minimum recommendation for a simple and consistent comparison of the mean threshold voltage (Vth) BTI induced shift. The procedure enables comparison of stable and manufacturable CMOS processes and technologies in which the process variation is low and the yield is mature. Qualification and accept-reject criteria are not given in this document. Committee(s): JC-14.2 Free download. Registration or login required. |
||
PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS:Status: Rescinded |
JESD92 | Aug 2003 |
JESD92 was rescinded by the committee in June 2024 and has been superseded by JESD263. This document defines a constant voltage stress test procedure for characterizing time-dependent dielectric breakdown or 'wear-out' of thin gate dielectrics used in integrated circuit technologies. The test is designed to obtain voltage and temperature acceleration parameters required to estimate oxide life at use conditions. The test procedure includes sophisticated techniques to detect breakdown in ultra-thin films that typically exhibit large tunneling currents and soft or noisy breakdown characteristics. This document includes an annex that discusses test structure design, methods to determine the oxide electric field in ultra-thin films, statistical models, extrapolation models, and example failure-rate calculations |
||
PRECONDITIONING OF NONHERMETIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING |
JESD22-A113I | Apr 2020 |
This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation. These SMDs should be subjected to the appropriate preconditioning sequence of this document by the semiconductor manufacturer prior to being submitted to specific in-house reliability testing (qualification and reliability monitoring) to evaluate long term reliability (which might be impacted by solder reflow). Committee(s): JC-14.1 Free download. Registration or login required. |