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WIRE BOND SHEAR TEST

 JESD22-B116B May 2017

This fully revised test provides a means for determining the strength of gold and copper ball bonds to a die or package bonding surface, and may be performed on pre-encapsulation or post-encapsulation parts. Pictures have been added to enhance the fail mode diagrams. The wire bond shear test is destructive. The test method can also be used to shear aluminum and copper wedge bonds to a die or package bonding surface. It is appropriate for use in process development, process control and/or quality assurance.

Committee(s): JC-14, JC-14.1

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Wire Bond Pull Test Methods

 JESD22-B120.01 Sep 2024

This test method provides a means for determining the strength and failure mode of a wire bonded to, and the corresponding interconnects on, a die or package bonding surface and may be performed on pre-encapsulation or post-encapsulation devices. 

Committee(s): JC-14, JC-14.1

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VIBRATION, VARIABLE FREQUENCY

 JESD22-B103B.01 Sep 2016

The Vibration, Variable Frequency Test Method is intended to determine the ability of component(s) to withstand moderate to severe vibration as a result of motion produced by transportation or filed operation of electrical equipment. This is a destructive test that is intended for component qualification. This is a minor editorial change to JESD22-B103B, June 2002 (Reaffirmed September 2010).

Committee(s): JC-14.1

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THERMAL SHOCK

 JESD22-A106B.02 Jan 2023

This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes.

Committee(s): JC-14, JC-14.1

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TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES

 JESD217A.01 Nov 2022

This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures.

Committee(s): JC-14.1

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Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications

 JESD22-B121 Nov 2023

This test method covers X-ray imaging for terrestrial applications on packaged devices.

Committee(s): JC-14, JC-14.1

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TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES

 JESD22-A120C Jan 2022

This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow.

Committee(s): JC-14.1

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TEST METHOD FOR REAL-TIME SOFT ERROR RATE

 JESD89-1B Jul 2021

This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources.

Committee(s): JC-14, JC-14.1

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TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES

 JESD22-B130 Sep 2022

This test method is offered as a standardized procedure to determine the total dose limit of DRAMs by measuring its refresh time tRef degradation after the device is irradiated with an X-Ray dose. This test method is applicable to any packaged device that contains a DRAM die or any embedded DRAM structure. Some indirect test methods such as wafer level characterization of total dose induced changes in leakage of access transistors are not described in this standard but are permissible as long as a good correlation is established.

Committee(s): JC-14.1

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TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE

 JESD89-3B Sep 2021

This test is used to determine the terrestrial cosmic ray Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g., flip-flops) by measuring the error rate while the device is irradiated in a neutron or proton beam of known flux. The results of this accelerated test can be used to estimate the terrestrial cosmic ray induced SER for a given terrestrial cosmic ray radiation environment. This test cannot be used to project alpha-particle induced SER.

Committee(s): JC-14.1

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TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE

 JESD89-2B Jul 2021

This test method is offered as standardized procedure to determine the alpha particle Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flipflops) by measuring the error rate while the device is irradiated by a characterized, solid alph source.

Committee(s): JC-14, JC-14.1

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TEMPERATURE, BIAS, AND OPERATING LIFE

 JESD22-A108G Nov 2022

This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document.

Committee(s): JC-14, JC-14.1

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Temperature Cycling

 JESD22-A104F.01 Apr 2023

This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing.

Committee(s): JC-14.1

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SYMBOL AND LABEL FOR ELECTROSTATIC SENSITIVE DEVICES

Status: Reaffirmed October 1988, September 1996, September 2009, May 2018, October 2024 		JESD471 Feb 1980

This standard will be useful to anyone engaged in handling semiconductor devices and integrated circuits that are subject to permanent damage due to electrostatic potentials. The standard establishes a symbol and label that will gain the attention of those persons who might inflict electrostatic damage to the device. The label which is placed on the lowest practical level of packaging contains the words 'ATTENTION - OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES'. The symbol contained in this label, which may be used on the device itself, shows a hand in a triangle with a bar through it. Formerly known as EIA-471.

Committee(s): JC-14, JC-14.3

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SUPERSEDED BY THE TEST METHODS INDICATED BY 'JESD22-'

Status: Superseded 		JESD22- B Jan 2000

A complete set of test methods can be obtained from Global Engineering Documents

Committee(s): JC-14.1

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

 JESD47L Dec 2022

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

Committee(s): JC-14, JC-14.3

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STEADY-STATE TEMPERATURE-HUMIDITY BIAS LIFE TEST

 JESD22-A101D.01 Jan 2021

This standard establishes a defined method and conditions for performing a temperature-humidity life test with bias applied. The test is used to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs high temperature and humidity conditions to accelerate the penetration of moisture through external protective material or along interfaces between the external protective coating and conductors or other features that pass through it. This revision enhances the ability to perform this test on a device which cannot be biased to achieve very low power dissipation.

Committee(s): JC-14, JC-14.1

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Statistical Process Control Systems

 JESD557D May 2023

This standard specifies the general requirements of a statistical process control (SPC) system. 
This is a revision of JESD557C.

Committee(s): JC-14

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STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALS

Status: Reaffirmed 04/17/2023 		JESD87 Apr 2023

This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems.

Committee(s): JC-14.2, JC-14.21

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STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE:

Status: Reaffirmed October 2012, September 2018 		JESD33B Feb 2004

This newly revised test method provides a procedure for measuring the temperature coefficient of resistance, TCR(T), of thin-film metallizations used in microelectronic circuits and devices. Procedures are also provided to use the TCR(T) to determine the temperature of a metallization line under Joule-heating conditions and to determine the ambient temperature where the metallization line is used as a temperature sensor. Originally, the method was intended only for aluminum-based metallizations and for other metallizations that satisfy the linear dependence and stability stipulations of the method. The method has been revised to make it explicitly applicable to copper-based metallizations, as well, and at temperatures beyond where the resistivity of copper is no longer linearly dependent on temperature (beyond approximately 200 °C). Using the TCR(T) measured for copper in the linear-dependent region, a factor is used to correct the calculated temperature at these higher temperatures.

Committee(s): JC-14.2

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