Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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ELECTRICAL PARAMETERS ASSESSMENTStatus: Reaffirmed May 2014, September 2020 |
JESD86A | Oct 2009 |
This standard is intended to describe various methods for obtaining electrical variate data on devices currently produced on the manufacturing and testing process to be qualified. The intent is to assess the device's capability to function within the specification parameters over time and the application environment (operating range of temperature, voltage, humidity, input/output levels, noise, power supply stability etc.). Committee(s): JC-14.3 Free download. Registration or login required. |
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ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TESTStatus: Reaffirmed October 2024 |
JESD22-A117E | Nov 2018 |
This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94. Free download. Registration or login required. |
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ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING HUMAN BODY MODEL (HBM)Status: Supersededby ANSI/ESDA/JEDEC JS-001, April 2010. |
JESD22-A114F | Dec 2008 |
This test method establishes a standard procedure for testing and classifying microcircuits according to their susceptibility to damage or degradation by exposure to a defined electrostatic Human Body Model (HBM) discharge (ESD). The objective is to provide reliable, repeatable HBM ESD test results so that accurate classifications can be performed. Committee(s): JC-14.1 |
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ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM)This document is inactive as of September 2016 |
JESD22-A115C | Nov 2010 |
JESD22-A115 is a reference document; it is not a requirement per JESD47 (Stress Test Driven Qualification of Integrated Circuits). Machine Model (MM) as described in JESD22-A115 should not be used as a requirement for integrated circuit ESD qualification. Only human-body model (HBM) and charged-device model (CDM) are the necessary ESD qualification test methods as specified in JESD47. Refer to JEP172: Discontinuing Use of the Machine Model for Device ESD Qualification for more information. Committee(s): JC-14.1 |
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ENVIRONMENTAL ACCEPTANCE REQUIREMENTS FOR TIN WHISKER SUSCEPTIBILITY OF TIN AND TIN ALLOY SURFACE FINISHEDStatus: Reaffirmed May 2014, January 2020 |
JESD201A | Sep 2008 |
The methodology described in this document is applicable for environmental acceptance testing of tin based surface finishes and mitigation practices for tin whiskers. This methodology may not be sufficient for applications with special requirements, (i.e., military, aerospace, etc.). Additional requirements may be specified in the appropriate requirements (procurement) documentation. Free download. Registration or login required. |
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EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES |
JESD22-A111B | Mar 2018 |
The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for small SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification. Free download. Registration or login required. |
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EXTERNAL VISUAL |
JESD22-B101D | Apr 2022 |
External visual inspection is an examination of the external surfaces, construction, marking, and workmanship of a finished package or component. External visual is a noninvasive and nondestructive test. It is functional for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required. |
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FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORINGStatus: Reaffirmed June 2011, May 2022 |
JESD659C | Apr 2017 |
This method establishes requirements for application of Statistical Reliability Monitoring 'SRM' technology to monitor and improve the reliability of electronic components and subassemblies. The standard also describes the condition under with a monitor may be replaced or eliminated. Formerly known as EIA-659, that superseded JESD29-A (July 1996). Became JESD659 after revision, September 1999. Free download. Registration or login required. |
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FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING - SUPERSEDED BY EIA/ANSI-659, July 1996.Status: Superseded |
JESD29-A | Jul 1996 |
Committee(s): JC-14.3 Free download. Registration or login required. |
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FAILURE-MECHANISM-DRIVEN RELIABILITY QUALIFICATION OF SILICON DEVICESStatus: Rescinded, November 2004 |
JESD34 | Mar 1993 |
This document applies to the reliability qualification of new or changed silicon devices, and their materials or manufacturing processes. Does not address qualification of product quality or functionality. Provides an alternative to traditional stress-driven qualification. Committee(s): JC-14.2 Free download. Registration or login required. |
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FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTSStatus: Rescinded February 2020 |
JESD22-C101F | Oct 2013 |
The material in this test method has been superseded by JS-002-2018, published January 2019, which in turn has been superseded by JS-002-2022, published January 2023. |
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FLIP CHIP TENSILE PULL |
JESD22-B109C | Mar 2021 |
The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test. Committee(s): JC-14.1 Free download. Registration or login required. |
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Gate Dielectric Breakdown |
JESD263 | Mar 2024 |
This document describes procedures developed for estimating the overall integrity of gate dielectrics. JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, JESD35-2 and JESD92. Free download. Registration or login required. |
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GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES |
JESD31F | Aug 2021 |
This standard identifies the general requirements for Distributors that supply Commercial and Military products. This standard applies to all discrete semiconductors, integrated circuits and Hybrids, whether packaged or in wafer/die form, manufactured by all Manufacturers. The requirements defined within this document are only applicable to products for which ownership remains with the Distributor or Manufacturer. Free download. Registration or login required. |
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HERMETICITYStatus: Reaffirmed September 2017 |
JESD22-A109B | Nov 2011 |
Testing for hermeticity on commercial product is not normally done on standard molded devices that are not hermetic. Commercial product that this test method applies to has a construction that produces a hermetic package; examples of this are ceramic and metal packages. Most of these tests are controlled and updated in the military standards, the two standards that apply are MIL-STD-750 for discretes, & MIL-STD-883 for microcircuits. The test within these standards can be used for all package types. Within these standards the tests are similar; MIL-STD-750 Test Method 1071 Hermetic Seal is recommended for any commercial hermetic requirements. For MIL-STD-883 the applicable test method is 1014 Seal. Committee(s): JC-14.1 Free download. Registration or login required. |
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HIGH TEMPERATURE CONTINUITYStatus: Rescinded November 1999 |
JESD22-C100-A | Jan 1990 |
Committee(s): JC-14.1 |
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HIGH TEMPERATURE STORAGE LIFE |
JESD22-A103E.01 | Jul 2021 |
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any). Committee(s): JC-14.1 Available for purchase: $55.00 Add to Cart Paying JEDEC Members may login for free access. |
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HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST) |
JESD22-A110E.01 | May 2021 |
The purpose of this test method is to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs severe conditions of temperature, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors which pass through it. This is a minor editorial edit to JESD22A110E, July 2015 approved by the formulating committee. Committee(s): JC-14.1 Free download. Registration or login required. |
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HYBRIDS/MCM |
JESD93A | May 2023 |
This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence. Committee(s): JC-14.3 Free download. Registration or login required. |
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IC LATCH-UP TEST |
JESD78F.02 | Nov 2023 |
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Free download. Registration or login required. |