Standards & Documents Search

Displaying 41 - 60 of 100 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST Status: Reaffirmed October 2024	JESD22-A117E	Nov 2018
This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
DEVICE QUALITY PROBLEM ANALYSIS AND CORRECTIVE ACTION RESOLUTION METHODOLOGY	JESD671D	Oct 2018
This standard addresses any Customer-initiated device problem analysis/corrective action request and Supplier/Authorized Distributor-identified device nonconformance to specification which may impact the Customer. This standard establishes a common set of Customer, Authorized Distributor and Supplier expectations and requirements that will help to facilitate successful problem analysis and corrective action of device problems, including administrative quality problems, which may affect the Customer. Formerly known as EIA-671 (November 1996). Became JESD671-A after revision, December 1999. Committee(s): JC-14.4 Free download. Registration or login required.
MECHANICAL COMPRESSIVE STATIC STRESS TEST METHOD	JESD22-B119	Oct 2018
This test method is intended for customers to determine the ability of a device to withstand the mechanical compressive static stress generated when a heat sink is being initially attached to the device, and to help the customer generate design rules for their heat sink design and validate their thermal solution. This test method does not assess the long-term effects of static stress. Committee(s): JC-14.1 Free download. Registration or login required.
BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICs FOR HANDHELD ELECTRONIC PRODUCTS	JESD22-B113B	Aug 2018
The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of surface mount electronic components in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of surface mounted components while duplicating the failure modes normally observed during product level test. This is not a component qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES	JESD22-A111B	Mar 2018
The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for small SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENT Status: Reaffirmed	JESD50C	Jan 2018
This standard applies to the identification and control of Maverick Product that can occur during fabrication, assembly, packaging, or test of any electronic component. It can be implemented for an entire product line or to segregate product that has a higher probability of adversely impacting quality or reliability. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING	JESD214.01	Aug 2017
This document describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method may be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time. Committee(s): JC-14.2 Free download. Registration or login required.
STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD:	JESD37A	Aug 2017
This standard details techniques for estimating the values of a two parameter lognormal distribution from complete lifetime data (all samples in an experiment have failed) or singly right-censored lifetime data (the experiment have failed) or singly right-censored lifetime data gathered from rapid stress test; however, not all types of failure data can be analyzed with these techniques. Committee(s): JC-14.2 Free download. Registration or login required.
WIRE BOND SHEAR TEST	JESD22-B116B	May 2017
This fully revised test provides a means for determining the strength of gold and copper ball bonds to a die or package bonding surface, and may be performed on pre-encapsulation or post-encapsulation parts. Pictures have been added to enhance the fail mode diagrams. The wire bond shear test is destructive. The test method can also be used to shear aluminum and copper wedge bonds to a die or package bonding surface. It is appropriate for use in process development, process control and/or quality assurance. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING Status: Reaffirmed June 2011, May 2022	JESD659C	Apr 2017
This method establishes requirements for application of Statistical Reliability Monitoring 'SRM' technology to monitor and improve the reliability of electronic components and subassemblies. The standard also describes the condition under with a monitor may be replaced or eliminated. Formerly known as EIA-659, that superseded JESD29-A (July 1996). Became JESD659 after revision, September 1999. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
LEAD INTEGRITY Status: Reaffirmed - May 2023	JESD22-B105E	Feb 2017
This test method provides various tests for determining the integrity lead/package interface and the lead itself when the lead(s) are bent due to faulty board assembly followed by rework of the part for reassembly. For hermetic packages it is recommend that this test be followed by hermeticity tests in accordance with Test Method A109 to determine if there are any adverse effects from the stresses applied to the seals as well as to the leads. These tests, including each of its test conditions, is considered destructive and is only recommended for qualification testing. This test is applicable to all through-hole devices and surface-mount devices requiring lead forming by the user. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICES Status: Reaffirmed February 2023	JESD22-B106E	Nov 2016
This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. Committee(s): JC-14.1 Free download. Registration or login required.
VIBRATION, VARIABLE FREQUENCY	JESD22-B103B.01	Sep 2016
The Vibration, Variable Frequency Test Method is intended to determine the ability of component(s) to withstand moderate to severe vibration as a result of motion produced by transportation or filed operation of electrical equipment. This is a destructive test that is intended for component qualification. This is a minor editorial change to JESD22-B103B, June 2002 (Reaffirmed September 2010). Committee(s): JC-14.1 Free download. Registration or login required.
SOLDER BALL PULL Status: Reaffirmed September 2021	JESD22-B115A.01	Jul 2016
This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. This is a minor editorial revision to JESD22-A115A. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
PROCEDURE FOR WAFER-LEVEL DC CHARACTERIZATION OF BIAS TEMPERATURE INSTABILITIES Status: Reaffirmed September 2021	JESD241	Dec 2015
This Bias Temperature Instability (BTI) stress/test procedure is proposed to provide a minimum recommendation for a simple and consistent comparison of the mean threshold voltage (Vth) BTI induced shift. The procedure enables comparison of stable and manufacturable CMOS processes and technologies in which the process variation is low and the yield is mature. Qualification and accept-reject criteria are not given in this document. Committee(s): JC-14.2 Free download. Registration or login required.
LOW TEMPERATURE STORAGE LIFE Status: Reaffirmed May 2021	JESD22-A119A	Oct 2015
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices Low Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). During the test reduced temperatures (test conditions) are used without electrical stress applied. This test may be destructive, depending on Time, Temperature and Packaging (if any). Committee(s): JC-14.1 Free download. Registration or login required.
APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGY Status: Reaffirmed January 2021	JESD94B	Oct 2015
The method described in this document applies to all application specific reliability testing for solid state components with known failure mechanisms where the test duration and conditions vary based on application variables. This document does not cover reliability tests that are characterization based or essentially go / no-go type tests, for example, ESD, latch-up, or electrical over stress. Also, it does not attempt to cover every failure mechanism or test environment, but does provide a methodology that can be extended to other failure mechanisms and test environments. Committee(s): JC-14.3 Free download. Registration or login required.
ACCELERATED MOISTURE RESISTANCE - UNBIASED AUTOCLAVE Status: Reaffirmed January 2021	JESD22-A102E	Jul 2015
This test allows the user to evaluate the moisture resistance of nonhermetic packaged solid state devices. The Unbiased Autoclave Test is performed to evaluate the moisture resistance integrity of non-hermetic packaged solid state devices using moisture condensing or moisture saturated steam environments. It is a highly accelerated test that employs conditions of pressure, humidity and temperature under condensing conditions to accelerate moisture penetration through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors passing through it. This test is used to identify failure mechanisms internal to the package and is destructive. Committee(s): JC-14.1 Free download. Registration or login required.
SOLDER BALL SHEAR Status: Reaffirmed September 2020	JESD22-B117B	May 2014
The purpose of this test is conducted to assess the ability of solder balls to withstand mechanical shear forces that may be applied during device manufacturing, handling, test, shipment and end-use conditions. Solder ball shear is a destructive test. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
RELIABILITY QUALIFICATION OF POWER AMPLIFIER MODULES Status: Reaffirmed October 2024	JESD237	Mar 2014
This standard is intended to identify a core set of qualification tests that apply specifically for Power Amplifier Modules and their primary application in mobile devices such as cellular phones. This standard is intended to describe specific stresses and failure mechanisms that are specific to compound semiconductors and power amplifier modules. It is intended to establish more meaningful and efficient qualification testing. Committee(s): JC-14.7 Free download. Registration or login required.

Pages

JEDEC Education Series: Memory, Mobile & Modules