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Title	Document #	Date
SYMBOL AND LABEL FOR ELECTROSTATIC SENSITIVE DEVICES Status: Reaffirmed October 1988, September 1996, September 2009, May 2018, October 2024	JESD471	Feb 1980
This standard will be useful to anyone engaged in handling semiconductor devices and integrated circuits that are subject to permanent damage due to electrostatic potentials. The standard establishes a symbol and label that will gain the attention of those persons who might inflict electrostatic damage to the device. The label which is placed on the lowest practical level of packaging contains the words 'ATTENTION - OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES'. The symbol contained in this label, which may be used on the device itself, shows a hand in a triangle with a bar through it. Formerly known as EIA-471. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
HIGH TEMPERATURE CONTINUITY Status: Rescinded November 1999	JESD22-C100-A	Jan 1990
Committee(s): JC-14.1
FAILURE-MECHANISM-DRIVEN RELIABILITY QUALIFICATION OF SILICON DEVICES Status: Rescinded, November 2004	JESD34	Mar 1993
This document applies to the reliability qualification of new or changed silicon devices, and their materials or manufacturing processes. Does not address qualification of product quality or functionality. Provides an alternative to traditional stress-driven qualification. Committee(s): JC-14.2 Free download. Registration or login required.
ADDENDUM No. 1 to JESD35, GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS Status: Rescinded	JESD35-1	Sep 1995
JESD35-1 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests. Committee(s): JC-14.2
MOISTURE-INDUCED STRESS SENSITIVITY FOR PLASTIC SURFACE MOUNT DEVICES - SUPERSEDED BY J-STD-020A, April 1999. Status: Rescinded, May 2000	JESD22-A112-A	Nov 1995
J-STD-020 is now on revision F. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
STANDARD FOR FAILURE ANALYSIS REPORT FORMAT: Status: Rescinded January 2025	JESD38	Dec 1995
This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional objectives are to ensure that reports can be easily ready by users, satisfactorily reproduced on copying machines, adequately transmitted by telefax, and conveniently stored in standard filing cabinets. Committee(s): JC-14.4 Free download. Registration or login required.
ADDENDUM No. 2 to JESD35 - TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS: Status: Rescinded	JESD35-2	Feb 1996
JESD35-2 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum includes test criteria to supplement JESD35. JESD35 describes procedures developed for estimating the overall integrity of thin oxides in the MOS Integrated Circuit manufacturing industry. Two test procedures are included in JESD35: a Voltage-Ramp (V-Ramp) and a Current-Ramp (J-Ramp). As JESD35 became implemented into production facilities on a variety of test structures and oxide attributes, a need arose to clarify end point determination and point out some of the obstacles that could be overcome by careful characterization of the equipment and test structures. Committee(s): JC-14.2
FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING - SUPERSEDED BY EIA/ANSI-659, July 1996. Status: Superseded	JESD29-A	Jul 1996
Committee(s): JC-14.3 Free download. Registration or login required.
COMPONENT PROBLEM ANALYSIS AND CORRECTIVE ACTION REQUIREMENTS - SUPERSEDED BY EIA-671, November 1996. Status: Superseded	JESD43	Nov 1996
Committee(s): JC-14.4 Free download. Registration or login required.
QUALITY SYSTEM ASSESSMENT - SUPERSEDED BY ANSI/EIA-670, June 1997. Status: Superseded	JESD39-A	Jun 1997
Committee(s): JC-14.4 Free download. Registration or login required.
SUPERSEDED BY THE TEST METHODS INDICATED BY 'JESD22-' Status: Superseded	JESD22- B	Jan 2000
A complete set of test methods can be obtained from Global Engineering Documents Committee(s): JC-14.1
PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS: Status: Rescinded	JESD35A	Apr 2001
JESD35A was rescinded by the committee in June 2024 and has been superseded by JESD263. The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown. Committee(s): JC-14.2
Addendum No. 1 to JESD28, N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS	JESD28-1	Sep 2001
This addendum provides data analysis examples useful in analyzing MOSFET n-channel hot-carrier-induced degradation data. This addendum to JESD28 (Hot carrier n-channel testing standard) suggests hot-carrier data analysis techniques. Committee(s): JC-14.2 Free download. Registration or login required.
A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS:	JESD28-A	Dec 2001
This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process. Committee(s): JC-14.2 Free download. Registration or login required.
OUTLIER IDENTIFICATION AND MANAGEMENT SYSTEM FOR ELECTRONIC COMPONENTS, RESCINDED January 2009. Replaced by JESD50. Status: RescindedJanuary 2009	JESD62-A	May 2002
Relevant JESD62 content has been consolidated into JESD50B, published October 2008 -Special Requirments for Maverick Product Elimination-. Committee(s): JC-14.3 Free download. Registration or login required.
PHYSICAL DIMENSION: Status: ReaffirmedJune 2006, January 2016, September 2021	JESD22-B100B	Jun 2003
The standard provides a method for determining whether the external physical dimensions of the device are in accordance with the applicable procurement document. This revision includes a change in details to be specified by the procurement document. Committee(s): JC-14.1 Free download. Registration or login required.
PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS: Status: Rescinded	JESD92	Aug 2003
JESD92 was rescinded by the committee in June 2024 and has been superseded by JESD263. This document defines a constant voltage stress test procedure for characterizing time-dependent dielectric breakdown or 'wear-out' of thin gate dielectrics used in integrated circuit technologies. The test is designed to obtain voltage and temperature acceleration parameters required to estimate oxide life at use conditions. The test procedure includes sophisticated techniques to detect breakdown in ultra-thin films that typically exhibit large tunneling currents and soft or noisy breakdown characteristics. This document includes an annex that discusses test structure design, methods to determine the oxide electric field in ultra-thin films, statistical models, extrapolation models, and example failure-rate calculations Committee(s): JC-14, JC-14.2
STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE: Status: Reaffirmed October 2012, September 2018	JESD33B	Feb 2004
This newly revised test method provides a procedure for measuring the temperature coefficient of resistance, TCR(T), of thin-film metallizations used in microelectronic circuits and devices. Procedures are also provided to use the TCR(T) to determine the temperature of a metallization line under Joule-heating conditions and to determine the ambient temperature where the metallization line is used as a temperature sensor. Originally, the method was intended only for aluminum-based metallizations and for other metallizations that satisfy the linear dependence and stability stipulations of the method. The method has been revised to make it explicitly applicable to copper-based metallizations, as well, and at temperatures beyond where the resistivity of copper is no longer linearly dependent on temperature (beyond approximately 200 °C). Using the TCR(T) measured for copper in the linear-dependent region, a factor is used to correct the calculated temperature at these higher temperatures. Committee(s): JC-14.2 Free download. Registration or login required.
MARKING, SYMBOLS, AND LABELS FOR IDENTIFICATION OF LEAD (Pb) FREE ASSEMBLIES, COMPONENTS, AND DEVICES - SUPERSEDED BY J-STD-609, August 2007 Status: Supersededby J-STD-609, August 2007	JESD97	May 2004
Committee(s): JC-14.1, JC-14.4 Free download. Registration or login required.
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS:	JESD60A	Sep 2004
This method establishes a standard procedure for accelerated testing of the hot-carrier-induced change of a p-channel MOSFET. The objective is to provide a minimum set of measurements so that accurate comparisons can be made between different technologies. The measurements specified should be viewed as a starting pint in the characterization and benchmarking of the trasistor manufacturing process. Committee(s): JC-14.2 Free download. Registration or login required.

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