Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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Addendum No. 1 to JESD28, N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS |
JESD28-1 | Sep 2001 |
This addendum provides data analysis examples useful in analyzing MOSFET n-channel hot-carrier-induced degradation data. This addendum to JESD28 (Hot carrier n-channel testing standard) suggests hot-carrier data analysis techniques. Committee(s): JC-14.2 Free download. Registration or login required. |
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ADDENDUM No. 1 to JESD35, GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICSStatus: Rescinded |
JESD35-1 | Sep 1995 |
JESD35-1 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests. Committee(s): JC-14.2 |
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ADDENDUM No. 2 to JESD35 - TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS:Status: Rescinded |
JESD35-2 | Feb 1996 |
JESD35-2 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum includes test criteria to supplement JESD35. JESD35 describes procedures developed for estimating the overall integrity of thin oxides in the MOS Integrated Circuit manufacturing industry. Two test procedures are included in JESD35: a Voltage-Ramp (V-Ramp) and a Current-Ramp (J-Ramp). As JESD35 became implemented into production facilities on a variety of test structures and oxide attributes, a need arose to clarify end point determination and point out some of the obstacles that could be overcome by careful characterization of the equipment and test structures. Committee(s): JC-14.2 |
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APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGYStatus: Reaffirmed January 2021 |
JESD94B | Oct 2015 |
The method described in this document applies to all application specific reliability testing for solid state components with known failure mechanisms where the test duration and conditions vary based on application variables. This document does not cover reliability tests that are characterization based or essentially go / no-go type tests, for example, ESD, latch-up, or electrical over stress. Also, it does not attempt to cover every failure mechanism or test environment, but does provide a methodology that can be extended to other failure mechanisms and test environments. Committee(s): JC-14.3 Free download. Registration or login required. |
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BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICs FOR HANDHELD ELECTRONIC PRODUCTS |
JESD22-B113B | Aug 2018 |
The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of surface mount electronic components in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of surface mounted components while duplicating the failure modes normally observed during product level test. This is not a component qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly. Free download. Registration or login required. |
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