Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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ELECTRICAL PARAMETERS ASSESSMENTStatus: Reaffirmed May 2014, September 2020 |
JESD86A | Oct 2009 |
This standard is intended to describe various methods for obtaining electrical variate data on devices currently produced on the manufacturing and testing process to be qualified. The intent is to assess the device's capability to function within the specification parameters over time and the application environment (operating range of temperature, voltage, humidity, input/output levels, noise, power supply stability etc.). Committee(s): JC-14.3 Free download. Registration or login required. |
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ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TESTStatus: Reaffirmed October 2024 |
JESD22-A117E | Nov 2018 |
This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94. Free download. Registration or login required. |
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ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING HUMAN BODY MODEL (HBM)Status: Supersededby ANSI/ESDA/JEDEC JS-001, April 2010. |
JESD22-A114F | Dec 2008 |
This test method establishes a standard procedure for testing and classifying microcircuits according to their susceptibility to damage or degradation by exposure to a defined electrostatic Human Body Model (HBM) discharge (ESD). The objective is to provide reliable, repeatable HBM ESD test results so that accurate classifications can be performed. Committee(s): JC-14.1 |
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ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM)This document is inactive as of September 2016 |
JESD22-A115C | Nov 2010 |
JESD22-A115 is a reference document; it is not a requirement per JESD47 (Stress Test Driven Qualification of Integrated Circuits). Machine Model (MM) as described in JESD22-A115 should not be used as a requirement for integrated circuit ESD qualification. Only human-body model (HBM) and charged-device model (CDM) are the necessary ESD qualification test methods as specified in JESD47. Refer to JEP172: Discontinuing Use of the Machine Model for Device ESD Qualification for more information. Committee(s): JC-14.1 |
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ENVIRONMENTAL ACCEPTANCE REQUIREMENTS FOR TIN WHISKER SUSCEPTIBILITY OF TIN AND TIN ALLOY SURFACE FINISHEDStatus: Reaffirmed May 2014, January 2020 |
JESD201A | Sep 2008 |
The methodology described in this document is applicable for environmental acceptance testing of tin based surface finishes and mitigation practices for tin whiskers. This methodology may not be sufficient for applications with special requirements, (i.e., military, aerospace, etc.). Additional requirements may be specified in the appropriate requirements (procurement) documentation. Free download. Registration or login required. |
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EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES |
JESD22-A111B | Mar 2018 |
The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for small SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification. Free download. Registration or login required. |
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EXTERNAL VISUAL |
JESD22-B101D | Apr 2022 |
External visual inspection is an examination of the external surfaces, construction, marking, and workmanship of a finished package or component. External visual is a noninvasive and nondestructive test. It is functional for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required. |
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FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORINGStatus: Reaffirmed June 2011, May 2022 |
JESD659C | Apr 2017 |
This method establishes requirements for application of Statistical Reliability Monitoring 'SRM' technology to monitor and improve the reliability of electronic components and subassemblies. The standard also describes the condition under with a monitor may be replaced or eliminated. Formerly known as EIA-659, that superseded JESD29-A (July 1996). Became JESD659 after revision, September 1999. Free download. Registration or login required. |
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FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING - SUPERSEDED BY EIA/ANSI-659, July 1996.Status: Superseded |
JESD29-A | Jul 1996 |
Committee(s): JC-14.3 Free download. Registration or login required. |
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FAILURE-MECHANISM-DRIVEN RELIABILITY QUALIFICATION OF SILICON DEVICESStatus: Rescinded, November 2004 |
JESD34 | Mar 1993 |
This document applies to the reliability qualification of new or changed silicon devices, and their materials or manufacturing processes. Does not address qualification of product quality or functionality. Provides an alternative to traditional stress-driven qualification. Committee(s): JC-14.2 Free download. Registration or login required. |
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