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Title	Document #	Date
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST Status: Reaffirmed October 2024	JESD22-A117E	Nov 2018
This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
DEVICE QUALITY PROBLEM ANALYSIS AND CORRECTIVE ACTION RESOLUTION METHODOLOGY	JESD671D	Oct 2018
This standard addresses any Customer-initiated device problem analysis/corrective action request and Supplier/Authorized Distributor-identified device nonconformance to specification which may impact the Customer. This standard establishes a common set of Customer, Authorized Distributor and Supplier expectations and requirements that will help to facilitate successful problem analysis and corrective action of device problems, including administrative quality problems, which may affect the Customer. Formerly known as EIA-671 (November 1996). Became JESD671-A after revision, December 1999. Committee(s): JC-14.4 Free download. Registration or login required.
MECHANICAL COMPRESSIVE STATIC STRESS TEST METHOD	JESD22-B119	Oct 2018
This test method is intended for customers to determine the ability of a device to withstand the mechanical compressive static stress generated when a heat sink is being initially attached to the device, and to help the customer generate design rules for their heat sink design and validate their thermal solution. This test method does not assess the long-term effects of static stress. Committee(s): JC-14.1 Free download. Registration or login required.
BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICs FOR HANDHELD ELECTRONIC PRODUCTS	JESD22-B113B	Aug 2018
The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of surface mount electronic components in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of surface mounted components while duplicating the failure modes normally observed during product level test. This is not a component qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES	JESD22-A111B	Mar 2018
The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for small SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENT Status: Reaffirmed	JESD50C	Jan 2018
This standard applies to the identification and control of Maverick Product that can occur during fabrication, assembly, packaging, or test of any electronic component. It can be implemented for an entire product line or to segregate product that has a higher probability of adversely impacting quality or reliability. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING	JESD214.01	Aug 2017
This document describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method may be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time. Committee(s): JC-14.2 Free download. Registration or login required.
STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD:	JESD37A	Aug 2017
This standard details techniques for estimating the values of a two parameter lognormal distribution from complete lifetime data (all samples in an experiment have failed) or singly right-censored lifetime data (the experiment have failed) or singly right-censored lifetime data gathered from rapid stress test; however, not all types of failure data can be analyzed with these techniques. Committee(s): JC-14.2 Free download. Registration or login required.
WIRE BOND SHEAR TEST	JESD22-B116B	May 2017
This fully revised test provides a means for determining the strength of gold and copper ball bonds to a die or package bonding surface, and may be performed on pre-encapsulation or post-encapsulation parts. Pictures have been added to enhance the fail mode diagrams. The wire bond shear test is destructive. The test method can also be used to shear aluminum and copper wedge bonds to a die or package bonding surface. It is appropriate for use in process development, process control and/or quality assurance. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING Status: Reaffirmed June 2011, May 2022	JESD659C	Apr 2017
This method establishes requirements for application of Statistical Reliability Monitoring 'SRM' technology to monitor and improve the reliability of electronic components and subassemblies. The standard also describes the condition under with a monitor may be replaced or eliminated. Formerly known as EIA-659, that superseded JESD29-A (July 1996). Became JESD659 after revision, September 1999. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.

Standards & Documents Search

ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

DEVICE QUALITY PROBLEM ANALYSIS AND CORRECTIVE ACTION RESOLUTION METHODOLOGY

MECHANICAL COMPRESSIVE STATIC STRESS TEST METHOD

BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICs FOR HANDHELD ELECTRONIC PRODUCTS

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES

SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENT

CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING

STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD:

WIRE BOND SHEAR TEST

FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING

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