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Title	Document #	Date
Wire Bond Pull Test Methods	JESD22-B120.01	Sep 2024
This test method provides a means for determining the strength and failure mode of a wire bonded to, and the corresponding interconnects on, a die or package bonding surface and may be performed on pre-encapsulation or post-encapsulation devices. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Board Level Drop Test Method of Components for Handheld Electronic Products	JESD22-B111A.01	Jun 2024
This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Information Requirements for the Qualification of Solid State Devices	JESD69D	Jun 2024
This standard defines the requirements for the device qualification package, which the supplier provides to the customer. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
Gate Dielectric Breakdown	JESD263	Mar 2024
This document describes procedures developed for estimating the overall integrity of gate dielectrics. JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, JESD35-2 and JESD92. Committee(s): JC-14, JC-14.2 Free download. Registration or login required.
Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices	JESD625C.01	Mar 2024
This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM). Committee(s): JC-13, JC-14.1 Free download. Registration or login required.
Power Cycling	JESD22-A122B	Nov 2023
This Test Method establishes a uniform method for performing solid state device package power cycling stress test. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature	JESD22-B112C	Nov 2023
This test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of thermal conditions experienced during the surface-mount soldering operation. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
IC LATCH-UP TEST	JESD78F.02	Nov 2023
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications	JESD22-B121	Nov 2023
This test method covers X-ray imaging for terrestrial applications on packaged devices. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Statistical Process Control Systems	JESD557D	May 2023
This standard specifies the general requirements of a statistical process control (SPC) system. This is a revision of JESD557C. Committee(s): JC-14 Free download. Registration or login required.

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JEDEC Education Series: Memory, Mobile & Modules