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This standard, JESD318-F0-RCE, “LPDDR5/5X Compression Attached Memory Module (CAMM2) Raw Card E Annex”, defines the design detail of eight x16 subchannels from four 315-ball dual channel LPDDR5/5x devices.

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Committee(s): JC-45

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This standard, JESD323-B4-RCD, “DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 CUDIMM) Raw Card D Annex” defines the design detail of x8, 1 Package Rank DDR5 ECC CUDIMM with Clock Driver.

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Committee(s): JC-45, JC-45.3

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This standard, JESD323-A0-RCA, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A Annex” defines the design detail of x8, 1 Package Rank DDR5 NECC CUDIMM with Clock Driver.

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Committee(s): JC-45, JC-45.3

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This standard, JESD324-V0-RCC, "DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) RawCard C Annex" defines the design detail of x16, 1 Package Ranks DDR5 CSODIMM with Clock Driver.

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Committee(s): JC-45.3

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This standard defines the Low Power Double Data Rate interface for Non-Volatile Memory (LPDDR4XNVM) Standard. This standard describes features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements

for a JEDEC compliant 16 bit single channel LPDDR4X-NVM device. LPDDR4X-NVM density ranges from 128Mb through 32Gb.

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Committee(s): JC-42, JC-42.6

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This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data.

Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits

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Committee(s): JC-14, JC-14.1

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This standard defines the form, fit and function of SODIMM DDR5 connectors for modules supporting channels with transfer rates 6.4 GT/S and beyond. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide performance standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR5 connectors in client and server platforms. Item 14-226

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Committee(s): JC-11, JC-11.14

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This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC).

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Committee(s): JC-40

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This standard provides a reference specification for systems and device management capabilities found in CXL memory devices. It is intended to target, but may not be limited to, CXL memory FRUs that are based on PCIe Gen 5 and compliant to the CXL 2.0 Specification or later.

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Committee(s): JC-40, JC-45

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This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications.

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Committee(s): JC-42

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The publication provides methodologies for measurements to qualify a new semiconductor wafer process.

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Committee(s): JC-14, JC-14.2

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Designator: PBGA-B#[#]_I80...

Item: 11-1064

Cross Reference: DR4.5

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Committee(s): JC-11, JC-11.11

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Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser.  Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32

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Committee(s): JC-64.8

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Designator:PDFN-N[#]_I1p27...

Item #: 11-1063

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Committee(s): JC-11, JC-11.11

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LPDDR5 CAMM2 Connector Performance Standard

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Committee(s): JC-11, JC-11.14

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Designator:  H-PDSO-G12_12p0-12p0x9p4Z2p8

Item No: 11-1049

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Committee(s): JC-11, JC-11.14

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Version 1.31

This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4).

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Committee(s): JC-42, JC-42.3

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Item 142.12

This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.

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Committee(s): JC-64.2

JESD21-C Solid State Memory Documents Main Page

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Designator:  XBNA-N#_I1p0_...

Item No:  14-229

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Committee(s): JC-11, JC-11.14

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This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices.

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Committee(s): JC-14, JC-14.1

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This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components.

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Committee(s): JC-14, JC-14.1

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This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb.

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Committee(s): JC-42, JC-42.6

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Item 11-1054

Package Designator: PQFP-N28_I4p0...

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Committee(s): JC-11, JC-11.10

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Item #11.5-1057

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Committee(s): JC-11, JC-11.5

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Designator: N/A

Item #: 11.5-1041

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Committee(s): JC-11, JC-11.5

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This document defines the standards for achieving Reliability certification and qualification of on-chip MIM Capacitors and MIS Trench Capacitors.

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Committee(s): JC-14, JC-14.2

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This document describes procedures developed for estimating the overall integrity of gate dielectrics.

JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, JESD35-2 and JESD92.

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Committee(s): JC-14, JC-14.2

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The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus.

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Committee(s): JC-42, JC-42.4

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This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM).

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Committee(s): JC-13, JC-14.1

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