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Title	Document #	Date
Serial Interface for Data Converters	JESD204D	Dec 2023
This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document. Committee(s): JC-16 Free download. Registration or login required.
XFM Device, Version 2.0	JESD233A	Dec 2023
This standard specifies the mechanical and electrical characteristics of the XFM removable memory Device. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-64, JC-64.1 Free download. Registration or login required.
Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices	JEP150A	Dec 2023
This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
Power Cycling	JESD22-A122B	Nov 2023
This Test Method establishes a uniform method for performing solid state device package power cycling stress test. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature	JESD22-B112C	Nov 2023
This test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of thermal conditions experienced during the surface-mount soldering operation. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
IC LATCH-UP TEST	JESD78F.02	Nov 2023
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications	JESD22-B121	Nov 2023
This test method covers X-ray imaging for terrestrial applications on packaged devices. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Zoned Storage for UFS	JESD220-5	Nov 2023
The purpose of this standard is to describe Zoned Storage for UFS, which enables higher bandwidth, lower latency and to reduce write amplification. Patents(): Huawei 201911209032.1; 116166570,A Memory Technologies LLC 101952808 104657284 2248023 3493067 602009056490.0 602009064847.0 HK1210296 5663720 6602823 10-1281326 10-1468824 2248023 3493067 2248023 3493067 8307180 8601228 9063850 9367486 10540094 11550476 Committee(s): JC-64, JC-64.1 Free download. Registration or login required.
Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension	JESD220-4 Version 1.01	Nov 2023
This standard specifies the extension specification of the UFS electrical interface and the memory device. PLEASE NOTE: Revision and renumbering of JESD231 Version 1.0, August 2022 Committee(s): JC-64, JC-64.1 Free download. Registration or login required.
Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices	JEP198	Nov 2023
This publication presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power switches. Committee(s): JC-70, JC-70.1 Free download. Registration or login required.
Guideline for Evaluating Bipolar Degradation of Silicon Carbide Power Devices	JEP197	Nov 2023
This publication provides guidance to SiC product suppliers and related power electronic industries in their evaluation of bipolar degradation mechanism in SiC power devices. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces	JEP196	Nov 2023
This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema	JEP181_Schema_R2p0	Nov 2023
In conjunction with JEP181A, for user support this file is the entire “XML Requirements Schema”. Committee(s): JC-15 Free download. Registration or login required.
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements	JEP181A	Nov 2023
This publication establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. Committee(s): JC-15 Free download. Registration or login required.
Design Requirements - BALL GRID ARRAY PACKAGE BALL PITCH ≤ 0.80 MM BODY SIZES ≤ 21 MM	DR-4.50	Nov 2023
BALL GRID ARRAY PACKAGE BALL PITCH ≤ 0.80 MM BODY SIZES ≤ 21 MM Item 2-1038 Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD)	JESD49B.01	Oct 2023
This standard facilitates the procurement and use of semiconductor die products provided in bare or bumped die form, and provides requirements and guidance to die suppliers as to the levels of as-delivered performance, quality and reliability expected. It also reflects the special needs of die product customers in terms of design and application data. Committee(s): JC-13 Free download. Registration or login required.
JEDEC COMMITTEE SCOPE MANUAL	JM18U	Oct 2023
The JEDEC Board of Directors is responsible for establishing appropriate committees to conduct its standardization activities. This publication identifies the service and product committees established by the Board of Directors and defines their scopes. Committee(s): JC-COUN Free download. Registration or login required.
Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification Release Number: 33	MODULE4.20.25.K.01	Aug 2023
This revision is to add R/C K1 for up to PC4-3200 support for the DDR4 SO-DIMM R/C K Annex. Item 2228.68. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PLASTIC QUAD FLATPACK 1.27 MM PITCH, 5.00 MM X 6.00 MM RECTANGULAR FAMILY PACKAGE	MO-356A	Aug 2023
Designator: PQFP-B#[#]_Ip27... Item #: 11-1037 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch Rectangular Family	MO-276U	Aug 2023
Designator: PBGA-B#[#]I0p5... Item JC11.11-1036 Cross Reference: DR4.5 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
TS511X, TS521X Serial Bus Thermal Sensor Device Standard	JESD302-1A	Aug 2023
This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document. Committee(s): JC-40.1 Free download. Registration or login required.
REGISTRATION - Upper PoP, Plastic Bottom Grid Array Ball, 0.40 mm Pitch Rectangular Family Package	MO-344B	Aug 2023
Designator: PBGA-B#[#]_I0p40... Item: 11.11-1035, Access Cross Reference: DR4.18 Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package	MO-341B	Aug 2023
Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1 Item: 11-1030 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES	JEP166E	Jul 2023
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories Committee(s): JC-42.6 Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X	JESD209-5C	Jul 2023
This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4). Committee(s): JC-42, JC-42.6 Available for purchase: $459.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
Registration - Plastic Quad Flatpack, 0.65 mm Pitch, 3.30 mm Body, Square Family Package	MO-346A.01	Jun 2023
Designator: PQFP-B#[#]_I0p65... Item: 11-981E, Access STP Files for MO-346A Cross Reference: N/A Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL	JS-002-2022	Jun 2023
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTS Status: Reaffirmed May 2023	JEP142	May 2023
This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests. Committee(s): JC-13, JC-13.5 Free download. Registration or login required.
Graphics Double Data Rate (GDDR6) SGRAM Standard	JESD250D	May 2023
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s): JC-42.3C Free download. Registration or login required.
Statistical Process Control Systems	JESD557D	May 2023
This standard specifies the general requirements of a statistical process control (SPC) system. This is a revision of JESD557C. Committee(s): JC-14 Free download. Registration or login required.
Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification	JEP114A	May 2023
This publication is a guideline to test facilities in their efforts to establish and maintain consistent particle impact noise detection (PIND) testing. Committee(s): JC-13, JC-13.5 Free download. Registration or login required.
Guidelines for Supplier Performance Rating	JEP146B	May 2023
This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria. Committee(s): JC-14, JC-14.4 Free download. Registration or login required.
HYBRIDS/MCM	JESD93A	May 2023
This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence. Committee(s): JC-14.3 Free download. Registration or login required.
SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD Release Number: Version 1.5.1	JESD300-5B.01	May 2023
This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard. Committee(s): JC-40.1 Free download. Registration or login required.
DDR4 NVDIMM-N Design Standard	JESD248A.01	Apr 2023
Terminology update. This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash. Committee(s): JC-45.6 Available for purchase: $123.36 Add to Cart Paying JEDEC Members may login for free access.
STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALS Status: Reaffirmed 04/17/2023	JESD87	Apr 2023
This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems. Committee(s): JC-14.2, JC-14.21 Free download. Registration or login required.
STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE: Status: Reaffirmed 4/17/23	JESD63	Apr 2023
This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process. Committee(s): JC-14.2 Free download. Registration or login required.
Registration - Shipping and Handling Tray for M.2 Type 2280 SSD Microelectronic Assembly	CO-038A	Apr 2023
Designator: N/A Item: 11.5-1001, Access STP File for CO-038A Cross Reference: N/A Committee(s): JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Shipping and Handling Tray for M.2 Type 2230 Microelectronic Assembly	CO-039A	Apr 2023
Designator: N/A Item: 11.5-1004, Access STP File for CO-039A Cross Reference: N/A Committee(s): JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
Temperature Cycling	JESD22-A104F.01	Apr 2023
This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing. Committee(s): JC-14.1 Free download. Registration or login required.
Registration - Plastic Quad Flat Package, Gull Wing and J-Lead, 0.65 MM Pitch	MO-355A	Apr 2023
Designator: PQFP-E#_I0p65-R... Item: 11.11-1028 Cross Reference: N/A Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Graphics Double Data (GDDR4) SGRAM Standard Release Number: 16	SDRAM3.11.5.8 R16.01	Mar 2023
Item 1600.41, Terminology Update This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics Random Access Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices. Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications	JESD82-27.01	Mar 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. Committee(s): JC-40 Free download. Registration or login required.
Fully Buffered DIMM Design for Test, Design for Validation (DFx)	JESD82-28A.01	Mar 2023
Terminology update. This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40, JC-40.5 Free download. Registration or login required.
RADIO FRONT END - BASEBAND DIGITAL PARALLEL (RBDP) INTERFACE	JESD207.01	Mar 2023
Terminology update. This document establishes an interface standard for the data path and control plane interface functions for an RFIC component and/or a BBIC component. Committee(s): JC-61 Free download. Registration or login required.
GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD	JESD232A.01	Mar 2023
Terminology update. This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package Committee(s): JC-42.3, JC-42.3C Free download. Registration or login required.
SILICON RECTIFIER DIODES:	JESD282B.02	Mar 2023
Terminology update. This legacy document is a comprehensive users’ guide for silicon rectifier diode applications. Committee(s): JC-22.2 Free download. Registration or login required.
DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS	JESD82-13A.01	Mar 2023
Terminology update. Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications Committee(s): JC-40 Free download. Registration or login required.
JEDEC Legal Guidelines	JM5.01	Mar 2023
Terminology update. This document sets forth the best judgment of the standards of conduct and legal restraints that must be observed to protect against violations of the law. Free download. Registration or login required.
COMPACT THERMAL MODEL OVERVIEW	JESD15-1.01	Mar 2023
Terminology update. This document should be used in conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
RADIO FRONT END - BASEBAND (RF-BB) INTERFACE	JESD96A.01	Mar 2023
Terminology update. This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC). Committee(s): JC-61 Free download. Registration or login required.
Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package	MO-210R	Mar 2023
Designator: PBGA-B#[#]_I0p... Item: 11.11-988, Access STP Files for MO-210R Cross Reference: DG4.5 https://www.jedec.org/filebrowser/download/1625 Patents(): May apply: Micron: 6,048,753. Tessera: 5,950,304; and 6,133,627 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Bottom Grid Array Ball, 0.40 MM Pitch Rectangular Family Package	MO-352A.01	Mar 2023
Designator: PBGA-B#[#}_I0p4... Item: 11.11-1006E (Minor editorial Change), Access STP File for MO-352A.01 Cross Reference: N/A Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
DDR5 Registering Clock Driver Definition (DDR5RCD03) Release Number: 1.00	JESD82-513	Feb 2023
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD03 Device ID is DID = 0x0053. Committee(s): JC-40, JC-40.5 Free download. Registration or login required.
Annex F, R/C F, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification Release Number: 33	MODULE4.20.26.F	Feb 2023
This specification defines the electrical and mechanical requirements for Raw Card F, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.43. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Guidelines for Packing and Labeling of Integrated Circuits in Unit Container Packing (Tubes, Trays, and Tape and Reel)	JEP130C	Feb 2023
This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality. Committee(s): JC-14, JC-14.4 Free download. Registration or login required.
DDR5 Registering Clock Driver Definition (DDR5RCD02) Release Number: Rev. 1.00	JESD82-512	Feb 2023
This standard defines specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD02 Device ID is DID = 0x0052. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion	JEP195	Feb 2023
This document elaborates on the information given in JEP184 regarding the long-time stability of device parameters under static conditions and under application near switching conditions. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs	JEP194	Feb 2023
This document provides guidelines for evaluating gate reliability and lifetime testing for silicon carbide (SiC) based power devices with a gate oxide or gate dielectric. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
DEFINITION OF THE SSTU32S869 AND SSTU32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-12A.01	Feb 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32S869 and SSTU32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. Committee(s): JC-40 Free download. Registration or login required.

Pages

JEDEC Education Series: Memory, Mobile & Modules

Standards & Documents Search

Serial Interface for Data Converters

XFM Device, Version 2.0

Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices

Power Cycling

Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature

IC LATCH-UP TEST

Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications

Zoned Storage for UFS

Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension

Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices

Guideline for Evaluating Bipolar Degradation of Silicon Carbide Power Devices

A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces

ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema

ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements

Design Requirements - BALL GRID ARRAY PACKAGE BALL PITCH ≤ 0.80 MM BODY SIZES ≤ 21 MM

PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD)

JEDEC COMMITTEE SCOPE MANUAL

Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

PLASTIC QUAD FLATPACK 1.27 MM PITCH, 5.00 MM X 6.00 MM RECTANGULAR FAMILY PACKAGE

Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch Rectangular Family

TS511X, TS521X Serial Bus Thermal Sensor Device Standard

REGISTRATION - Upper PoP, Plastic Bottom Grid Array Ball, 0.40 mm Pitch Rectangular Family Package

Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package

JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES

LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X

Registration - Plastic Quad Flatpack, 0.65 mm Pitch, 3.30 mm Body, Square Family Package

ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTS

Graphics Double Data Rate (GDDR6) SGRAM Standard

Statistical Process Control Systems

Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification

Guidelines for Supplier Performance Rating

HYBRIDS/MCM

SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD

DDR4 NVDIMM-N Design Standard

STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALS

STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:

Registration - Shipping and Handling Tray for M.2 Type 2280 SSD Microelectronic Assembly

Registration - Shipping and Handling Tray for M.2 Type 2230 Microelectronic Assembly

Temperature Cycling

Registration - Plastic Quad Flat Package, Gull Wing and J-Lead, 0.65 MM Pitch

Graphics Double Data (GDDR4) SGRAM Standard

Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications

Fully Buffered DIMM Design for Test, Design for Validation (DFx)

RADIO FRONT END - BASEBAND DIGITAL PARALLEL (RBDP) INTERFACE

GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD

SILICON RECTIFIER DIODES:

DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS

JEDEC Legal Guidelines

COMPACT THERMAL MODEL OVERVIEW

RADIO FRONT END - BASEBAND (RF-BB) INTERFACE

Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package

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