Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 CUDIMM) Raw Card E AnnexRelease Number: Version 1.00 |
JESD323-B4-RCE | Feb 2025 |
This annex, JESD323-B4-RCE, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card E Annex" defines the design detail of x8, 2 Package Ranks DDR5 CUDIMM. The common feature of DDR5 CUDIMM such as the connector pinout can be found in the JESD323, DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Standard. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common StandardRelease Number: Version 1.1 |
JESD323A | Feb 2025 |
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Clocked, Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CUDIMMs). These DDR5 Clocked Unbuffered DIMMs (CUDIMMs) are intended for use as main memory when installed in Computers. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common StandardRelease Number: Version 1.1 |
JESD324A | Feb 2025 |
This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Clocked Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CSODIMMs). These DDR5 CSODIMMs are intended for use as main memory when installed in Computers, laptops and other systems. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card A AnnexRelease Number: Version 2.00 |
JESD305-R8-RCA | Feb 2025 |
This annex, JESD305-R8-RCA, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card A Annex, defines the design detail of x4, 2 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card B AnnexRelease Number: Version 1.00 |
JESD323-A0-RCB | Feb 2025 |
This annex, JESD323-A0-RCB, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card B Annex", defines the design detail of x8, 2 Package Ranks DDR5 CUDIMM. The common feature of DDR5 CUDIMM such as the connector pinout can be found in the JESD323, DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Standard. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card B AnnexRelease Number: Version 1.00 |
JESD324-V0-RCB | Feb 2025 |
This annex JESD324-V0-RCB, “DDR5 Clocked Small Outline Dual Inline Memory Module with 0-bit ECC (EC0 CSODIMM) Raw Card B Annex" defines the design detail of x8, 2 Package Ranks DDR5 NECC Clocked SODIMM. The common feature of DDR5 CSODIMM such as the connector pinout can be found in the JESD324, DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Standard. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common StandardRelease Number: Version 1.2 |
JESD308B | Feb 2025 |
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common StandardRelease Number: Version 1.1 |
JESD309A | Feb 2025 |
This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM SODIMMs). These DDR5 SODIMMs are intended for use as main memory when installed in Computers, laptops and other systems. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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Graphics Double Data Rate 7 SGRAM Standard (GDDR7) |
JESD239B | Feb 2025 |
This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.
A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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PMIC5120 Power Management IC StandardRelease Number: Version 1.0 |
JESD301-6 | Feb 2025 |
This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5120 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5120 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Unless otherwise noted in the document, any illegal operation is not allowed and device operation is not guaranteed. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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