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Displaying 1 - 6 of 6 documents. Show 5 results per page.

Title	Document #	Date
IPC/JEDEC-9704A: PRINTED WIRING BOARD (PWB) STRAIN GAGE TEST GUIDELINE	JS9704A	Jan 2012
This document describes specific guidelines for strain gage testing for Printed Wiring Board (PWB)assemblies. The suggested procedures enables board manufacturers to conduct required strain gage testing independently, and provides a quantitative method for measuring board flexure, and assessing risk levels. The topics covered include: Test setup and equipment; requirements; Strain measurement; Report format Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
IPC/JEDEC-9703: MECHANICAL SHOCK TEST GUIDELINE FOR SOLDER JOINT RELIABILITY Status: Reaffirmed May 2014, May 2019	JS9703	Mar 2009
This document establishes mechanical shock test guidelines for assessing solder joint reliability of Printed Circuit Board (PCB) assemblies from system to component level. Committee(s): JC-14.1 Free download. Registration or login required.
Definition of “Low-Halogen” For Electronic Products	JS709D	Jan 2024
This standard provides terms and definitions for “low-halogen” electronic products. Committee(s): JC-14, JC-14.4 Free download. Registration or login required.
IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)	JS9702	Jun 2004
This publication specifies a common method of establishing the fracture resistance of board-level device interconnects to flexural loading during non-cyclic board assembly and test operations. Monotonic bend test qualification pass/fail requirements are typically specific to each device application and are outside the scope of this document. This version contains Addendum 1, May 2015, reposted 8/15/2016. Committee(s): JC-14.1 Free download. Registration or login required.
JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - COMPONENT LEVEL	JS-001-2023	Jul 2023
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data. Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL	JS-002-2022	Jun 2023
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.