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Title	Document #	Date
CLASSIFICATION OF PASSIVE AND SOLID STATE DEVICES FOR ASSEMBLY PROCESSES	J-STD-075A	May 2018
This is a Joint Standard between ECIA, IPC, and JEDEC. The purpose of this specification is to establish an agreed to set of worst case solder assembly process conditions to which devices are evaluated. The generated PSL rating will convey the conditions to which a device can be safely attached to FR4 type or ceramic laminates using SMT reflow and solder wave/fountain soldering processes. It is important for device manufacturers (hereafter referred to as “suppliers”), users, and (PWB) assemblers to be highly familiar with this standard’s information and processes to insure optimal device quality and reliability. THIS DOCUMENT IS NOT AVAILABLE FOR FREE DOWNLOAD. However, this document is available to the JEDEC formulating Committee members on the JC-14 Resources tab on the Members' website. The lead organization is ECIA. Committee(s): JC-14
JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)	J-STD-020F	Dec 2022
The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
JOINT JEDEC/IPC/ECIA STANDARD - NOTIFICATION STANDARD FOR PRODUCT DISCONTINUANCE	J-STD-048	Nov 2014
This document supersedes JESD48. This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. The goal of this notification standard is to better enable customers to manage and mitigate the disruption caused by the discontinuation of a product and ensure continuity of supply. This standard establishes the requirements for timely customer notification of planned product discontinuance, which will assist customers in managing end-of-life supply, or to transition ongoing requirements to alternate products. Committee(s): JC-14.4 Free download. Registration or login required.
SOLDERABILITY TESTS FOR COMPONENT LEADS, TERMINATIONS, LUGS, TERMINALS AND WIRES: Removed 01/21/04 Release Number: B	J-STD-002	Feb 2003
At the request of IPC, J-STD-002B has been removed from the free download area. In its place, JEDEC's Test Method, JESD22-B102, Solderability, which includes lead-free, was made available until it was replaced by J-STD-002D. Any revision to J-STD-002 will no longer be available for free to the industry on the JEDEC website. However, the document is available to the JEDEC formulating Committee members, in the Members Area. If you are not a JEDEC member you may wish to try the IPC website or one of the resellers listed at: http://www.jedec.org/standards-document Committee(s): JC-13, JC-14.1
Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly	J-STD-609C.01	Apr 2024
This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd level terminal finish or material. Committee(s): JC-14, JC-14.4 Free download. Registration or login required.
CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS	J-STD-046	Jul 2016
This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. This standard establishes the requirements for timely customer notification of changes to electronic products and associated processes. This document replaces JESD46. Committee(s): JC-14.4 Free download. Registration or login required.
ADDENDUM No. 1 to EIA-318 - CHARACTERIZATION OF A REVERSE TEST FIXTURE: SUPERSEDED BY EIA-318-B, July 1996. Status: Rescinded	EIA318-1	Feb 1981
Committee(s): JC-22.4 Free download. Registration or login required.
MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODES: Status: Reaffirmed	EIA318-B	Jul 1996
This standard describes the measurement of signal diodes (IF <=500mA dc) reverse recovery times of less than 300 ns duration. It may, however, also be used for the measurement of longer recovery times. This standard is also intended to establish a method which to characterize the test fixture used for this measurement. Committee(s): JC-22.4 Free download. Registration or login required.
AIR-CONVECTION-COOLED, LIFE TEST ENVIRONMENT FOR LEAD-MOUNTED SEMICONDUCTOR DEVICES: Status: ReaffirmedFebruary 1972, November 2002	EIA323	Mar 1966
This standard is applicable to life testing of lead-mounted semiconductor devices intended for applications in a natural air-cooled environment where most of the power dissipation is obtained by convection and radiation losses from the body to the device. Committee(s): JC-22.1 Free download. Registration or login required.
PERFORMANCE TEST PROCEDURE FOR SOLAR CELLS AND CALIBRATION PROCEDURE FOR SOLAR CELL STANDARDS FOR SPACE VEHICLE SERVICE: Status: ReaffirmedFebruary 1984	EIA365	Nov 1969
The purpose of this standard is to classify the output of solar cells for space vehicle service in accordance with requirements of EIA Format JS4-RDF4. Committee(s): JC-23.1 Free download. Registration or login required.
ADDENDUM No. 1 TO EIA-397:	EIA397-1	Jul 1980
A compilation of 12 new or revised thyristor test methods which have been adopted since the original standard was issued in 1972. Committee(s): JC-22.1 Free download. Registration or login required.
RECOMMENDED STANDARD FOR THYRISTORS:	EIA397	Jun 1972
One section of this standard presents a thorough explanation of thyristor principals, defining thedifferent classes of these devices, their Physical structure and detailing the numerous test methods and ratings required in their application to electronic and power circuitry. Another section presents a universally accepted listing of letter symbols. Considerable effort is devoted to the use of JEDEC Type Registration System as related to thyristors. This will permit the device manufacturer to employ a uniform procedure in the development of maximum rating and presentation of performance data. Committee(s): JC-22.1 Free download. Registration or login required.
NATIONAL ELECTRONIC PROCESS CERTIFICATION STANDARD; GOVERNMENT CONTRACTORS: Removed: August 25, 2003	EIA599-A	Jan 1998
Due to notification from the JC-14.4 subcommittee that the material contained in EIA599 has been replaced by the ISO 9000 series, the JEDEC Board of Directors, at its August 2003 meeting, approved to remove this standard from the JEDEC Free Download Area. Committee(s): JC-14.4
TYPE DESIGNATION SYSTEM FOR MICROELECTRONIC DEVICES Status: Rescinded September 1993	EIA428-A	Jan 1988
Committee(s): JC-10
PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS Status: Rescinded May 2006	EIA623	Jul 1994
Committee(s): JC-13 Free download. Registration or login required.
PREPARATION OF OUTLINE DRAWINGS OF SOLID-STATE PRODUCTS FOR JEDEC TYPE REGISTRATION, RESCINDED May 2009 Status: RescindedMay, 2009	EIA308-A	Aug 1981
Note that the terms and definitions contained in EIA308A are still available in the JEDEC dictionary as they are commonly used in the industry. Committee(s): JC-11 Free download. Registration or login required.
TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION: Status: Rescinded	JES2	Jul 1992
Establishes guideline requirements and quality assurance provisions for gallium arsenide power field-effect transistors (FETs, also know as MESFETs) designed for use in high-reliability space application such as spacecraft communications transmitters. Identifies the electrical parameters, wafer acceptance tests, screening tests, qualification tests, and lot acceptance tests pertinent to power GaAs FETs. Applicable to packaged and chip-carrier parts; portions may not be applicable to unpackaged and unmounted chips. **This document was rescinded on October 17, 2024, but is available for download for reference. purposes. Committee(s): JC-14.7 Free download. Registration or login required.
DDR4 DIMM Product Label, Hybrid, Pre-Production, DDR4E Release Number: 29	DIMM-LABEL4.19.4	Aug 2019
This section covers DDR4 and DDR4E in both DRAM-only module types and Hybrid module types, as well as pre-production modules of both types. Item 2224.13A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR DIMM Product Label Release Number: 28	DIMM-LABEL4.19-1	Dec 2018
Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Labeling Requirements for DDR Series DIMMs Release Number: 28	DIMM-LABEL4.19	Oct 2018
This standard provides the labels for the DDR Series DIMMs. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

Standards & Documents Search

CLASSIFICATION OF PASSIVE AND SOLID STATE DEVICES FOR ASSEMBLY PROCESSES

JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)

JOINT JEDEC/IPC/ECIA STANDARD - NOTIFICATION STANDARD FOR PRODUCT DISCONTINUANCE

SOLDERABILITY TESTS FOR COMPONENT LEADS, TERMINATIONS, LUGS, TERMINALS AND WIRES:

Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly

CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS

ADDENDUM No. 1 to EIA-318 - CHARACTERIZATION OF A REVERSE TEST FIXTURE: SUPERSEDED BY EIA-318-B, July 1996.

MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODES:

AIR-CONVECTION-COOLED, LIFE TEST ENVIRONMENT FOR LEAD-MOUNTED SEMICONDUCTOR DEVICES:

PERFORMANCE TEST PROCEDURE FOR SOLAR CELLS AND CALIBRATION PROCEDURE FOR SOLAR CELL STANDARDS FOR SPACE VEHICLE SERVICE:

ADDENDUM No. 1 TO EIA-397:

RECOMMENDED STANDARD FOR THYRISTORS:

NATIONAL ELECTRONIC PROCESS CERTIFICATION STANDARD; GOVERNMENT CONTRACTORS:

TYPE DESIGNATION SYSTEM FOR MICROELECTRONIC DEVICES

PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS

PREPARATION OF OUTLINE DRAWINGS OF SOLID-STATE PRODUCTS FOR JEDEC TYPE REGISTRATION, RESCINDED May 2009

TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION:

DDR4 DIMM Product Label, Hybrid, Pre-Production, DDR4E

DDR DIMM Product Label

Labeling Requirements for DDR Series DIMMs

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