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Title	Document #	Date
288 PIN DDR5 U/R/LR DIMM, 0.85 MM PITCH.	MO-329B	Apr 2020
Designator: PDMA-N288-I0p85-R133p8x5p57Z31p8R2p55x0p6 Item: 11.14-197, Access STP Files for MO-329B Cross Reference: SO-023, GS-010C Patents(): Micron: 7,547,213. Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
48 Lead, Very, Very Thin Small Outline Package, Type 1. WR-PDSO1, WSOP1. Item 11.11-701.	MO-259-A	Mar 2005
Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
ACCEPTED PRACTICES FOR MAKING MICROELECTRONIC DEVICE THERMAL CHARACTERISTICS TESTS Status: Rescinded	JEB20	Jan 1975
Committee(s): JC-11
ANNUAL UPDATING SERVICE:	JEP95 AUS	Jan 2000
Subscription to this updating service is available from the JEDEC Office. New outlines are shipped to subscribers for insertion into the appropriate sections of Publication No. 95. JEP95 and Updating Service can be ordered through JEDEC at (703)907-7540 or ptanner@jedec.org. Committee(s): JC-11
DDR4 260 Pin SODIMM Connector Performance Standard	PS-003A.01	Jul 2016
This standard defines the form, fit and function of SODIMM DDR4 connectors for modules supporting channels with transfer rates as high as 3.2 GT/S. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR4 connectors in client and server platforms. Item 11.14-179E Patents(): FOXCONN US PATENT NO.: 5,882,211; 6,126,472; 6,113,398 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
DDR5 DIMM SMT 288 PIN SOCKET OUTLINE 0.85 MM PITCH SKT	SO-023B	Jul 2019
Item 11.14-196 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
DESCRIPTIVE DESIGNATION SYSTEM FOR ELECTRONIC-DEVICE PACKAGES	JESD30I	Aug 2019
This standard establishes requirements for the generation of electronic-device package designators for the JEDEC Solid State Technology Association. The requirements herein are intended to ensure that such designators are presented in as uniform a manner as practicable. Item 11.2-962. Committee(s): JC-11.2 Free download. Registration or login required.
Design Requirements - Ball Grid Array (BGA)Package Measuring and Methodology.	DG-4.17C	Jul 2008
Item 11.2-791(S) Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Ball Grid Array Package (BGA)	DR-4.27F.01	Nov 2018
Ball Pitch = 0.65, 0.75 and 0.80 mm, Body sizes >21mm. (For body sizes ≤ 21mm see Design Registration 4.5) Item 11.2-969E. Editorial Change Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Ball Grid Array Package (BGA)	DR-4.14J.01	Feb 2019
Item 11.2-948E Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Ball Grid Array Package (BGA) and Interstitial Ball Grid Array Package (IBGA)	DR-4.5N.01	Nov 2018
Ball Pitch = 0.40, 0.50, 0.65, 0.75 and 0.80 mm. Body sizes = ≤ 21 mm.Item 11.2-968E, Editorial Change. Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Die-Size Ball Grid Array Packages (DSBGA) Design Guide.	DG-4.7F	Jan 2014
Item 11.2-829R Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Fine pitch, Rectangular Ball Grid Array Packages (FRBGA). Status: RescindedFebruary 2015	DR-4.6D.01	Jul 2012
This outline has been replaced by Design Registration 4.5J and Design Registration 4.27C. Item 11.2-838(S), 11-893R, 11-894R Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page
Design Requirements - Fine-Pitch, Land Grid Array Package, Square and Rectangular (FLGA, FRLGA)	DG-4.25B	Aug 2016
This Design Requirement defines the symbols, definitions, algorithms, and specified dimensions and tolerances for Fine-pitch, LGA packages. The guidelines defined are based on hard metric dimensions and adhere to the geometric dimensioning and tolerancing principles defined in ASME Y14.5M-1994. Item 11.2-896(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Fine-pitch, Square Ball Grid Array Package (FBGA) Package-on-Package (PoP).	DR-4.22C.02	Mar 2011
Item 11.2-839(R) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - General Requirements	DG-4.2	Jan 1980
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Generic Matrix Tray for Handling and Shipping (Low Stacking Profile for BGA Packages).	DG-4.9A	Mar 2000
Item 11.2-539S Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Generic Matrix Tray for Handling and Shipping, includes addition of optional side-wall bar code feature.	DG-4.10D	Oct 2002
Item 11.2-615s Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Internal Stacking Module, Land Grid Array Packages with External Interconnect Terminals (ISM).	DG-4.21A	Feb 2007
Item 11.2-699(S) Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Metric Small Outline J-Leaded Package Design Guide	DG-4.13	Aug 1996
Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Micropillar Grid Array (MPGA)	DR-4.26B	Nov 2015
Item 11.2-845(R) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (with Optional Thermal Enhancements). QFP-N/SO-N.	DG-4.8C	Sep 2006
Item 11.2-713(s) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Plastic Ultra-Thin Small outline No-Lead Package. R-PDSO-N/USON.	DG-4.16A	Feb 1998
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Punch-Singulated, Fine Pitch, Square, Very Thin and Very Very Thin Profile, Leadframe-Based Quad No-Lead Staggared Dual-Row Packages, (with optional Thermal Enhancements) QFN.	DG-4.23A	Nov 2005
Item 11.2-728(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Quad Flatpack	DG-4.4A	Jun 2000
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Quad No-Lead Staggered and Inline Multi-Row Packages (with optional thermal enhancements). QFN.	DG-4.19D	May 2007
Item 11.2-765(s) Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Scalable Quad Flat No-lead Packages, Square and Rectangular (Scalable QFN)	DG-4.24B	Aug 2016
Item 11.2-850(S) Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Small Scale Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (With Optional Thermal Enhancements). Small Scale (QFN/SON).	DG-4.20F	Sep 2016
Item 11.2-820(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Thin Small Outline Package, TSOP - Type 2.	DG-4.15B	May 2004
Item 11.2-675(s) Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Wafer Level Ball Grid Arrays (WLBGA).	DG-4.18A	Nov 2004
Item 11.2-647(s) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
DESIGN REQUIRMENTS FOR OUTLINES OF SOLID STATE AND RELATED PRODUCTS: DISCONTINUED AS A SEPARATE ITEM. NOW CONTAINED IN JEP95, BOOK 1, SECTION 4. Status: Incorporated	JESD95-1	Jan 2000
Committee(s): JC-11
JEDEC REGISTERED AND STANDARD OUTLINES FOR SOLID STATE AND RELATED PRODUCTS:	JEP95	Jan 2000
This publication is a compilation of some 1800 pages of outline drawings for microelectronic packages including transistors, diodes, DIPS, chip carriers and package interface BGA outlines in both inch and metric versions. Committee(s): JC-11 See JEP95 information
JEP95 Registrations Main Page	JEP95 Index	Apr 2001
This page will provide a link to the Master Index for JEP95. It also provides a link to 'index by device type' as well as the table of contents for each section within JEP95. For older outlines that have been archived, they can be accessed through this page. Committee(s): JC-11 JEP95 Registrations Main Page See JEP95 Index information
PART MODEL ASSEMBLY PROCESS CLASSIFICATION GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS	JEP30-A100	Feb 2018
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Assembly Process Classification” subsection of the Part Model. Committee(s): JC-11.2 Free download. Registration or login required.
PART MODEL ASSEMBLY PROCESS CLASSIFICATION SCHEMA	JEP30-A101X	Mar 2018
In conjunction with JEP30-A100, for user support this file is the entire “Part Model Assembly Process Classification Schema” (JEP30-10 Part Model Schema, JEP30-A101 Part Model Assembly Process Classification Schema, and JEP30-D10 Part Model Schema Types Dictionary). Committee(s): JC-11 Free download. Registration or login required.
PART MODEL ELECTRICAL GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS	JEP30-E100	Apr 2018
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model. Committee(s): JC-11.2 Free download. Registration or login required.
PART MODEL ELECTRICAL SCHEMA	JEP30-E101X	Apr 2018
In conjunction with JEP30-E100, for user support, this file is the entire “Part Model Electrical Schema” (JEP30-10 Part Model Schema, JEP30-e101 Part Model Thermal Schema, and JEP30-D10 Part Model Schema Types Dictionary). Committee(s): JC-11.2 Free download. Registration or login required.
PART MODEL GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS	JEP30	Feb 2018
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure. Committee(s): JC-11.2 Free download. Registration or login required.
PART MODEL PACKAGE GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS	JEP30-P100.01	May 2018
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Package" subsection of the Part Model. Committee(s): JC-11.2 Free download. Registration or login required.
PART MODEL PACKAGE SCHEMA	JEP30-P101X	Mar 2018
In conjunction with JEP30-P100, for user support thiis file is the entire “Part Model Package Schema” (JEP30-10 Part Model Schema, JEP30-P101 Part Model Package Schema, and JEP30-D10 Part Model Schema Types Dictionary). Committee(s): JC-11 Free download. Registration or login required.

Standards & Documents Search

288 PIN DDR5 U/R/LR DIMM, 0.85 MM PITCH.

48 Lead, Very, Very Thin Small Outline Package, Type 1. WR-PDSO1, WSOP1. Item 11.11-701.

ACCEPTED PRACTICES FOR MAKING MICROELECTRONIC DEVICE THERMAL CHARACTERISTICS TESTS

ANNUAL UPDATING SERVICE:

DDR4 260 Pin SODIMM Connector Performance Standard

DDR5 DIMM SMT 288 PIN SOCKET OUTLINE 0.85 MM PITCH SKT

DESCRIPTIVE DESIGNATION SYSTEM FOR ELECTRONIC-DEVICE PACKAGES

Design Requirements - Ball Grid Array (BGA)Package Measuring and Methodology.

Design Requirements - Ball Grid Array Package (BGA)

Design Requirements - Ball Grid Array Package (BGA)

Design Requirements - Ball Grid Array Package (BGA) and Interstitial Ball Grid Array Package (IBGA)

Design Requirements - Die-Size Ball Grid Array Packages (DSBGA) Design Guide.

Design Requirements - Fine pitch, Rectangular Ball Grid Array Packages (FRBGA).

Design Requirements - Fine-Pitch, Land Grid Array Package, Square and Rectangular (FLGA, FRLGA)

Design Requirements - Fine-pitch, Square Ball Grid Array Package (FBGA) Package-on-Package (PoP).

Design Requirements - General Requirements

Design Requirements - Generic Matrix Tray for Handling and Shipping (Low Stacking Profile for BGA Packages).

Design Requirements - Generic Matrix Tray for Handling and Shipping, includes addition of optional side-wall bar code feature.

Design Requirements - Internal Stacking Module, Land Grid Array Packages with External Interconnect Terminals (ISM).

Design Requirements - Metric Small Outline J-Leaded Package Design Guide

Design Requirements - Micropillar Grid Array (MPGA)

Design Requirements - Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (with Optional Thermal Enhancements). QFP-N/SO-N.

Design Requirements - Plastic Ultra-Thin Small outline No-Lead Package. R-PDSO-N/USON.

Design Requirements - Punch-Singulated, Fine Pitch, Square, Very Thin and Very Very Thin Profile, Leadframe-Based Quad No-Lead Staggared Dual-Row Packages, (with optional Thermal Enhancements) QFN.

Design Requirements - Quad Flatpack

Design Requirements - Quad No-Lead Staggered and Inline Multi-Row Packages (with optional thermal enhancements). QFN.

Design Requirements - Scalable Quad Flat No-lead Packages, Square and Rectangular (Scalable QFN)

Design Requirements - Small Scale Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (With Optional Thermal Enhancements). Small Scale (QFN/SON).

Design Requirements - Thin Small Outline Package, TSOP - Type 2.

Design Requirements - Wafer Level Ball Grid Arrays (WLBGA).

DESIGN REQUIRMENTS FOR OUTLINES OF SOLID STATE AND RELATED PRODUCTS: DISCONTINUED AS A SEPARATE ITEM. NOW CONTAINED IN JEP95, BOOK 1, SECTION 4.

JEDEC REGISTERED AND STANDARD OUTLINES FOR SOLID STATE AND RELATED PRODUCTS:

JEP95 Registrations Main Page

PART MODEL ASSEMBLY PROCESS CLASSIFICATION GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS

PART MODEL ASSEMBLY PROCESS CLASSIFICATION SCHEMA

PART MODEL ELECTRICAL GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS

PART MODEL ELECTRICAL SCHEMA

PART MODEL GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS

PART MODEL PACKAGE GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS

PART MODEL PACKAGE SCHEMA

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