Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
SPD Annex L, Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 4Release Number: 27A |
SPD4.1.2.L-4 | Aug 2019 |
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 4. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01G. This is an editorial revision to the publication in January 2017. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 29 |
MODULE4.20.25 | Aug 2019 |
This document defines the electrical and mechanical requirements for 260 pin, 1.2 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops and other systems. This document also contains the DDR4 DIMM Label, Ranks Definition. Item 2224.13A Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 29 |
MODULE4.20.26 | Aug 2019 |
This specification defines the electrical and mechanical requirements for the 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs are intended for use as main memory when installed in PCs. Item 2241.13A Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR4 DIMM Product Label, Hybrid, Pre-Production, DDR4ERelease Number: 29 |
DIMM-LABEL4.19.4 | Aug 2019 |
This section covers DDR4 and DDR4E in both DRAM-only module types and Hybrid module types, as well as pre-production modules of both types. Item 2224.13A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR4 DATA BUFFER DEFINITION (DDR4DB02) |
JESD82-32A | Aug 2019 |
This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. Item 314.11D *If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required. |
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THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP) |
JESD51-4A | Jul 2019 |
The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations. Committee(s): JC-15 Free download. Registration or login required. |
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0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05) |
JESD8-33 | Jun 2019 |
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03 Committee(s): JC-16 Free download. Registration or login required. |
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MECHANICAL SHOCK – DEVICE AND SUBASSEMBLY |
JESD22-B110B.01 | Jun 2019 |
Device and Subassembly Mechanical Shock Test Method is intended to evaluate devices in the free state and assembled to printed wiring boards for use in electrical equipment. The method is intended to determine the compatibility of devices and subassemblies to withstand moderately severe shocks. The use of subassemblies is a means to test devices in usage conditions as assembled to printed wiring boards. Mechanical Shock due to suddenly applied forces, or abrupt change in motion produced by handling, transportation or field operation may disturb operating characteristics, particularly if the shock pulses are repetitive. This is a destructive test intended for device qualification.This document also replaces JESD22-B104. Free download. Registration or login required. |
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288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design SpecificationRelease Number: 29 |
MODULE4.20.28 | May 2019 |
This specification defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2149.05E Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Registration - Silicon Bottom Grid Array Column, 0.048 x 0.0275 Pitch, Rectangular Family Package |
MO-316B | Apr 2019 |
Package Designator: SBGA-M#(#)_I0p055 Item Number: 11.4-966 Committee(s): JC-11.4 Free download. Registration or login required. |
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