Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C AnnexRelease Number: Version 1.00 |
JESD323-A0-RCC | Dec 2024 |
This standard, “JESD323-A0-RCC, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C Annex” defines the design detail of x16, 1 Package Ranks DDR5 Clocked UDIMM. Free download. Registration or login required. |
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LPDDR5 CAMM2, 1.38 MM X 1.00 MM PITCH MICROELECTRONIC ASSEMBLY |
MO-357D | Nov 2024 |
Designator: XBMA-H736_I1p0_R78p0x23p0Z2p6 Item #: 11.14-232 Free download. Registration or login required. |
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PLASTIC DUAL UPPER TO BOTTOM, 1.38 MM X1.00 MM PITCH CONNECTOR (CMT) |
SO-032D | Nov 2024 |
Designator: SO-032D_PDUtBXC-H736_I1p0-R17p15x78p0Z1p05 Patents(): Patent NO: 9,425,525 Free download. Registration or login required. |
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DDR5 DIMM Labels |
JESD401-5C | Nov 2024 |
This standard defines the labels that shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently. Committee(s): JC-45 Free download. Registration or login required. |
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288 TERM DDR5 DIMM, 0.85 MM PITCH, MICROELECTRONIC ASSEMBLY |
MO-329I | Nov 2024 |
Designator: PDMA-N288-I0p85-R136p8x5p57Z31p8R2p55x0p6 Item: 14-230 Cross Reference: MO-329, SO-023, GS-010
Patents(): Micron: US7,547,213. Free download. Registration or login required. |
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SILICON BOTTOM GRID ARRAY COLUMN, 0.035 MM X 0.055 MM PITCH RECTANGULAR PACKAGE |
MO-362A | Nov 2024 |
Designator: SBGA-M16148[49588]_D0p068... Item #: 4-1056
Committee(s): JC-11 Free download. Registration or login required. |
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Compression Attached Memory Module (CAMM2) Common Standard |
JESD318A Ver. 1.10 | Nov 2024 |
This standard defines the electrical and mechanical requirements for Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (DDR5 SDRAM CAMM2s) and Low Power Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (LP5 SDRAM CAMM2s). Committee(s): JC-45 Free download. Registration or login required. |
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LPDDR5/5X Compression Attached Memory Module (CAMM2) Raw Card E AnnexRelease Number: Version 1.00 |
JESD318-F0-RCE | Nov 2024 |
This standard, JESD318-F0-RCE, “LPDDR5/5X Compression Attached Memory Module (CAMM2) Raw Card E Annex”, defines the design detail of eight x16 subchannels from four 315-ball dual channel LPDDR5/5x devices. Committee(s): JC-45 Free download. Registration or login required. |
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DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card A AnnexRelease Number: Version 1.00 |
JESD324-V0-RCA | Nov 2024 |
This standard, JESD324-V0-RCA, “DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card A Annex” defines the design detail of x8, 1 Package Ranks DDR5 CSODIMM with Clock Driver. Free download. Registration or login required. |
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DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECCRelease Number: Version 1.00 |
JESD323-B4-RCD | Nov 2024 |
This standard, JESD323-B4-RCD, “DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 CUDIMM) Raw Card D Annex” defines the design detail of x8, 1 Package Rank DDR5 ECC CUDIMM with Clock Driver. Free download. Registration or login required. |