Global Standards for the Microelectronics Industry
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Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFSRelease Number: 32
File temporarily removed for correction. In the interim, to obtain a copy of Release number 31, contact Angie Steigleman.
This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.