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Title	Document #	Date
DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD	JEP152	May 2007
This document is the work product of the JC-45.1 DDR2 DIMM Clock Skew Measurement task group.The purpose of this document is to define procedures to measure clock parameters on registered DIMMs using the DDR2 Clock Reference Board. It is NOT the intent of this document to set specification values or validation requirements. Committee(s): JC-45, JC-45.1 Free download. Registration or login required.
Annex W, R/C W, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.07	MODULE4.20.20.W	Aug 2009
Release No. 19 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex Y, R/C Y, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.06	MODULE4.20.20.Y	Aug 2009
Release No. 19 Committee(s): JC-45.1, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
214-Pin DDR2 SDRAM Unbuffered MicroDIMM Design Specification	MODULE4.20.12	Apr 2004
Release No. 14 Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification	MODULE4.20.9	Nov 2004
Release No. 14 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

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