Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
JEDEC MODULE SIDEBAND BUS (SidebandBus) |
JESD403-1.01 | Jul 2021 |
This standard is a minor editorial revision to JESD403-1, it defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.37B. Committee(s): JC-45 Free download. Registration or login required. |
||
240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.19 | May 2021 |
Release No. 31. Item 2131.03, 2078.04, 2131.06This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.13 | May 2021 |
Release 31. Item 2167.05This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
PC-2700/PC-3200 Registered DIMM Design Specification Revision 2.2 |
MODULE4.20.7 | May 2021 |
Release 31. Item 2029.04This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
DDR4 NVDIMM-P BUS PROTOCOL |
JESD304-4.01 | Jan 2021 |
This version is a minor editorial adding Annex B that was left out of the original publication October 2020.An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory. A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K. Committee(s): JC-45.6 Free download. Registration or login required. |
||
Annex D, R/C D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design SpecificationRelease Number: 30 |
MODULE4.20.27.D | Dec 2020 |
This specification defines the electrical and mechanical requirements for Raw Card D, 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Item 2204.23 Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
Annex A, Raw Card A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design SpecificationRelease Number: 30 |
MODULE4.20.27.A | Dec 2020 |
Item No. 2204.22 Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 30A |
MODULE4.20.26.B | Dec 2020 |
This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.26. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
Annex D, R/C D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 30 |
MODULE4.20.26.D | Dec 2020 |
This document defines the electrical and mechanical requirements for Raw Card D, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.21A. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
Annex B, Raw Card B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design SpecificationRelease Number: 30 |
MODULE4.20.27.B | Dec 2020 |
This specification defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Item 2204.24. Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
