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DDR5 DIMM Labels

 JESD401-5B Aug 2023

The following labels shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently.

Committee(s): JC-45

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DDR5 SODIMM Raw Card Annex C Version 1

 JESD309-S0-RCC Jun 2022

This annex JESD309-S0-RCC, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Raw Card
C Annex defines the design detail of x16, 1 Package Ranks DDR5 SODIMM. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard.

Committee(s): JC-45, JC-45.3

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240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification

 MODULE4.20.19 May 2021

Release No. 31. Item 2131.03, 2078.04, 2131.06

This revision contains terminology updates only.

Committee(s): JC-45, JC-45.2, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification

 MODULE4.20.13 May 2021

Release 31.  Item 2167.05

This revision contains terminology updates only.

Committee(s): JC-45, JC-45.2, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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PC-2700/PC-3200 Registered DIMM Design Specification Revision 2.2

 MODULE4.20.7 May 2021

Release 31. Item 2029.04

This revision contains terminology updates only.

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Annex N, R/C N, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2145.22

 MODULE4.20.20.N Sep 2012

Release No. 22. Item 2145.35

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

MODULE4.20.20 Feb 2012

Release No. 22. Item 2082.94A

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Annex C, R/C C in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

 MODULE4.20.20.C May 2011

Release No. 21
Item 2082.38A, 2082.71, 2100.02, 2100.04

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Annex AB, R/C AB in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

 MODULE4.20.20.AB May 2011

Release No. 21
Item 2202.01

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Annex J, R/C J in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification.

MODULE4.20.20.J May 2011

Release No. 21

Item 2082.93

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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240-Pin PC2-6400/PC2-5300/PC2-4200/PC2-3200 DDR2 SDRAM Registered DIMM Design Standard, Rev 4.04.

MODULE4.20.10 Jan 2010

Release No. 19A.  Items 2133.37, 2191.00, 2191.02, 2129.12, 2113.33.

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Annex W, R/C W, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.07

 MODULE4.20.20.W Aug 2009

Release No. 19

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Annex Y, R/C Y, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.06

 MODULE4.20.20.Y Aug 2009

Release No. 19

Committee(s): JC-45.1, JC-45

JESD21-C Solid State Memory Documents Main Page

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200-Pin DDR2 SDRAM Unbuffered SODIMM Design Specification

 MODULE4.20.11 Jun 2008

Release No. 18. Item 2168.01

Committee(s): JC-45, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD

 JEP152 May 2007

This document is the work product of the JC-45.1 DDR2 DIMM Clock Skew Measurement task group.The purpose of this document is to define procedures to measure clock parameters on registered DIMMs using the DDR2 Clock Reference Board. It is NOT the intent of this document to set specification values or validation requirements.

Committee(s): JC-45, JC-45.1

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DDR3 Unbuffered MicroDIMM Design Specification, 214-Pin PC3-12800. Item 2031.04

 MODULE4.20.17 Mar 2007

Release No. 17

Committee(s): JC-45, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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PC2-4200/PC2-3200 DDR2 Registered Mini-DIMM Design Specification Revision 2.0

 MODULE4.20.14 Dec 2006

Release No. 16. Item 2105.00

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification

 MODULE4.20.9 Nov 2004

Release No. 14

Committee(s): JC-42, JC-45

JESD21-C Solid State Memory Documents Main Page

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DIMM Design Files

 DIMM Homepage Dec 2003

These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to downloading files. Design Files (Gerber Files) have been developed in accordance with the JEDEC Manual of Operation and Procedure.

Committee(s): JC-42, JC-45

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