Standards & Documents Search

Displaying 21 - 40 of 105 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE	JESD251-1.01	Sep 2021
This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus performance than legacy SPI memory implementations. Item 1775.15. This is an editorial revision to JESD251-1, October 2018 Committee(s): JC-42.4 Free download. Registration or login required.
PC-1600/PC-2100 DDR SDRAM Registered DIMM Design Specification (184 Pin)	MODULE4.20.4	May 2021
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPECIALITY DDR2-1066 SDRAM	JESD208	Nov 2007
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required.
ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)	JESD209-4-1A	Feb 2021
This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55A. Committee(s): JC-42.6 Available for purchase: $106.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
Serial NOR Security Hardware Abstraction Layer	JESD261	Nov 2022
This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device. Committee(s): JC-42.4 Free download. Registration or login required.
EEPROM, Word Wide	EEPROM3.5.2	Jun 2007
Release No. 16. Item 1704.1 Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Addendum No. 1 to JESD79-4, 3D STACKED DRAM	JESD79-4-1B	Feb 2021
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G Committee(s): JC-42.3C Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD	JESD209B	Feb 2010
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Patents(): See Document Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required.
168 Pin, PC-133 SDRAM Registered DIMM Design Specification	MODULE4.20.2	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide SDRAM	SDRAM3.11.3	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide EEPROM	EEPROM3.5.1	Aug 2005
Release No. 14 Committee(s): JC-42.4, JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
STANDARD MANUFACTURERS IDENTIFICATION CODE	JEP106BK	Sep 2024
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
Nibble Wide SDRAM	SDRAM3.11.2	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide SRAM	SRAM3.7.5	Apr 2003
Release No.12 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)	JESD229	Dec 2011
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. Committee(s): JC-42, JC-42.6 Free download. Registration or login required.
SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)	JESD255	Mar 2024
The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
COMMON FLASH INTERFACE (CFI):	JESD68.01	Sep 2003
The Common Flash Interface (CFI) specification outlines a device and host system software interrogation handshake that allows specific software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specific flash families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. The changes for this minor revision are indicated in Annex A on page 11. Committee(s): JC-42.4 Free download. Registration or login required.
Word Wide DRAM	DRAM3.9.4	Jul 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 This is a minor editorial revision, the differences between revisions can be found on page 17 of the document.	JESD79-3-1A.01	May 2013
The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard. The purpose of this standard is to define the DDR3L specifications that supersede the DDR3 specifications as defined in JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, and DDR3L-1866 titles in JESD79-3 are to be interpreted as DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 respectively, when applying towards DDR3L definition; unless specifically stated otherwise. Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
SPD Annex J: Serial Presence Detect for DDR2 SDRAM	SPD4.1.2.10	Jan 2007
Release No. 17 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

Standards & Documents Search

Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE

PC-1600/PC-2100 DDR SDRAM Registered DIMM Design Specification (184 Pin)

SPECIALITY DDR2-1066 SDRAM

ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)

Serial NOR Security Hardware Abstraction Layer

EEPROM, Word Wide

Addendum No. 1 to JESD79-4, 3D STACKED DRAM

LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD

168 Pin, PC-133 SDRAM Registered DIMM Design Specification

Byte Wide SDRAM

Byte Wide EEPROM

STANDARD MANUFACTURERS IDENTIFICATION CODE

Nibble Wide SDRAM

Byte Wide SRAM

WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)

SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)

COMMON FLASH INTERFACE (CFI):

Word Wide DRAM

Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866

SPD Annex J: Serial Presence Detect for DDR2 SDRAM

Pages

Current search

Search found 105 items

Search by Keyword or Document Number

Filter by committees:

Filter by document type:

Filter by keywords: