Global Standards for the Microelectronics Industry
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Document # | Date |
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Low Power Double Data Rate (LPDDR) Non-Volatile Memory (NVM) (Item 1674.17, 1674.16, 1674.20 |
NVRAM3.6.3 | Feb 2009 |
Release No. 18A JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X |
JESD209-5C | Jul 2023 |
This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4). Available for purchase: $459.00 Add to Cart Paying JEDEC Members may login for free access. |
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JESD21C, Section 6, Applicable other documents for JESD21C |
JESD21C.6 | Mar 2008 |
Release No. 17 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES |
JEP166E | Jul 2023 |
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories Committee(s): JC-42.6 Free download. Registration or login required. |
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High Speed DDR SRAM in 165 BGA |
SRAM3.7.10 | Feb 2008 |
Release No. 17. Item 1755 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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HIGH BANDWIDTH MEMORY (HBM3) DRAM |
JESD238A | Jan 2023 |
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Free download. Registration or login required. |
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HIGH BANDWIDTH MEMORY (HBM) DRAM |
JESD235D | Mar 2021 |
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L. Committee(s): JC-42.3C Available for purchase: $247.00 Add to Cart Paying JEDEC Members may login for free access. |
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Graphics Double Data Rate 7 SGRAM Standard (GDDR7) |
JESD239A | Sep 2024 |
This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.
Free download. Registration or login required. |
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Graphics Double Data Rate (GDDR6) SGRAM Standard |
JESD250D | May 2023 |
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s): JC-42.3C Free download. Registration or login required. |
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GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD |
JESD232A.01 | Mar 2023 |
Terminology update. This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package Committee(s): JC-42.3, JC-42.3C Free download. Registration or login required. |
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GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARDRelease Number: C.01 - Terminology update |
JESD212C.01 | Jan 2023 |
Terminology update. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3C Free download. Registration or login required. |
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Graphics Double Data (GDDR4) SGRAM StandardRelease Number: 16 |
SDRAM3.11.5.8 R16.01 | Mar 2023 |
Item 1600.41, Terminology Update This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics Random Access Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices. Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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General SDRAM Functions |
SDRAM3.11.5.1 | Jun 2002 |
Release No. 12 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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GDDR5 MEASUREMENT PROCEDURES |
JEP171 | Aug 2014 |
This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5. Committee(s): JC-42.3 Free download. Registration or login required. |
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GDDR3 Specific SGRAM Functions |
SDRAM3.11.5.7 | May 2005 |
Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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GDDR2 Specific SGRAM Functions |
SDRAM3.11.5.6 | May 2005 |
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Four Byte Modules and Cards Table of Contents |
MODULE4.4.TOC | Jun 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES |
JESD251C | May 2022 |
This standard specifies the eXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, which provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is primarily for use in computing, automotive, Internet Of Things (IOT), embedded systems and mobile systems, between host processing and peripheral devices. The xSPI electrical interface can deliver up to 400 MBytes per second raw data throughput. Item 1775.74. Committee(s): JC-42.4 Free download. Registration or login required. |
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EPROM Introduction |
EPROM3.4 | Jul 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Enhanced SDRAM (ESDRAM) Specific SDRAM Functions |
SDRAM3.11.5.3 | Jun 1999 |
Release No. 9 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Eight Byte Wide (X64/72) MOS SRAM |
SRAM3.7.9 | Jun 2007 |
Release No. 16A. Item 1480.05 and 1531.04 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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EEPROM, Word Wide |
EEPROM3.5.2 | Jun 2007 |
Release No. 16. Item 1704.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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EEPROM Extended Features |
EEPROM3.5.3 | Jan 2005 |
Release No.14 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Dynamic Random Access Memory (DRAM) Table of Contents |
DRAM3.9.TOC | Jul 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Dual Inline Memory Modules (DIMMs) Table of Contents |
MODULE4.20.TOC | Dec 2014 |
Release No. 24 Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DRAM Operational Features |
DRAM3.9.5 | Feb 2000 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Double Word Wide MOS SRAM |
SRAM3.7.8 | Apr 2007 |
Release No. 16. Item 1541.03 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DOUBLE DATA RATE (DDR) SDRAM STANDARD |
JESD79F | Feb 2008 |
This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices. Committee(s): JC-42.3 Free download. Registration or login required. |
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DIMM Design Files |
DIMM Homepage | Dec 2003 |
These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to downloading files. Design Files (Gerber Files) have been developed in accordance with the JEDEC Manual of Operation and Procedure. |
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Device Specification Annex for JESD21-C |
SDRAM3.2 | Apr 2003 |
Release No.12 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications |
SPD4.1.6-01 | May 2022 |
Release 26.01, Terminology update This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROM (EE) and Temperature Sensor (TS) as used for memory module applications. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications |
SPD4.1.4-01 | May 2022 |
Release No. 21.01, Terminology update. This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROMs and Temperature Sensor (TS) as used for memory module applications. The designation TSE2002av refers to the family of devices specified by this document. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs |
SPD4.1.3-01 | May 2022 |
Release No. 19.01. Item 1739.02E, Terminology update. This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROMs as used for memory module applications. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD |
JESD404-1 | Nov 2020 |
Definition for all DDRx component documents to reference. This is generic to any DDRx Committee(s): JC-42.3C Free download. Registration or login required. |
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DDR5 SDRAMRelease Number: Version 1.31 |
JESD79-5C.01 | Jul 2024 |
Version 1.31 This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4). Available for purchase: $423.00 Add to Cart Paying JEDEC Members may login for free access. |
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DDR4 SDRAM STANDARD |
JESD79-4D | Jul 2021 |
This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78H Committee(s): JC-42.3C Available for purchase: $284.00 Add to Cart Paying JEDEC Members may login for free access. |
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DDR3 SDRAM STANDARD |
JESD79-3F | Jul 2012 |
This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3 Available for purchase: $247.00 Add to Cart Paying JEDEC Members may login for free access. |
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DDR2 Specific SDRAM Function |
SDRAM3.11.5.5 | Jul 2008 |
Release No. 18 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION |
JEP179 | Jun 2006 |
The purpose of this document is to explain the meaning of SPD setting (JESD21 SPD section) for DDR2 SDRAM (JESD79-2) in normal and extended temperature operationy67. Committee(s): JC-42.3 Free download. Registration or login required. |
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DDR2 SDRAM STANDARD |
JESD79-2F | Nov 2009 |
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Free download. Registration or login required. |
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DDR Specific SDRAM Functions |
SDRAM3.11.5.2 | Jun 2003 |
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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CONFIGURATIONS FOR SOLID STATE MEMORIES:Status: Under RevisionSections in this document may be under revision at any time. |
JESD21-C | Jan 2003 |
This revision of JESD21 is substantially different from previous issues because it reflects advancement in semiconductor technology and computer design needs. A new class of memory devices, the multiport DRAM (MPDRAM) C also know as 'Video Ram' because of the most common application for the devices C is represented. A new family of SRAMs which addresses the increasing need for high speed is introduced. Additional families of devices in the SOJ and Zip packages are included. The material in this revision is organized primarily by function (ROM, EPROM, SRAM, DRAM, etc.) rather than by technology and word length. Pinouts for SIMM and DIMM are included along with presence detect schemes. A current set of terms has also been included. JESD21-C is a compilation of all memory device standards that have been developed by the JC-42 Committee and approved by the JEDEC BoD from September 1989 to present. This latest issue has changed to a loose-leaf format and comes in a three-ring binder so that new drawings can be added without requiring a new publication. Time of publication of the material is identified by release number, i.e., if marked Release 8, this item was approved and released in 1998, if marked Release 13, this item was approved and released in 2003. Committee(s): JC-42 |
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COMMON FLASH INTERFACE (CFI): |
JESD68.01 | Sep 2003 |
The Common Flash Interface (CFI) specification outlines a device and host system software interrogation handshake that allows specific software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specific flash families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. The changes for this minor revision are indicated in Annex A on page 11. Committee(s): JC-42.4 Free download. Registration or login required. |
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COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODES: |
JEP137B | May 2004 |
This publication is a companion document to the Common Flash Interface (CFI) standard, JESD68, which outlines the device and host system software interrogation handshake. JEP137 documents ID Code assignments for: 1)) the Algorithm-specific Command Set and Control Interfaces and 2) the Device Interfaces. It is published as needed when additions are made to either of these lists of codes. To make a request for an ID Code please contact the JEDEC Office at (703)907-7558. Committee(s): JC-42.4 Free download. Registration or login required. |
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Byte Wide SRAM |
SRAM3.7.5 | Apr 2003 |
Release No.12 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide SDRAM |
SDRAM3.11.3 | Jan 2004 |
Release No.13 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide ROM |
ROM3.2.1 | Dec 1992 |
Release No.2 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide PROM |
PROM3.3.2 | Dec 1993 |
Release No.1 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide MPDRAM |
MPDRAM3.10.2 | Jun 1997 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide EEPROM |
EEPROM3.5.1 | Aug 2005 |
Release No. 14 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide ECL SRAM |
SRAM3.7.6 | Jul 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide DRAM |
DRAM3.9.3 | Jun 1999 |
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide |
EPROM3.4.1 | Jul 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Bit Wide TTL SRAM |
SRAM3.7.1 | Dec 1995 |
Release No. 5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Bit Wide SDRAM |
SDRAM3.11.1 | Jun 1997 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Bit Wide ECL SRAM |
SRAM3.7.2 | Jul 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Bit Wide DRAM |
DRAM3.9.1 | Jun 1999 |
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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ANNUAL UPDATING SERVICE: |
JESD21-C AUS | Jan 2004 |
The JEDEC Office has generated a mailing list for those who wish to subscribe to updates of this publication. A payment is required for subscription to this updating service. Committee(s): JC-42 |
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Annex A: Differences between JESD21C Release 29 and its predecessor JESD21C, Release 28.Release Number: 29 |
AnnexA - JESD21C | Jan 2020 |
This table briefly describes the changes made to this standard, JESD21-C, Release 29, compared to its predecessor, JESD21C, Release 28. Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Addendum No. 3 to JESD79-3, 3D STACKED SDRAM |
JESD79-3-3 | Dec 2013 |
This addendum to JESD79-3 defines the 3DS DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for compliant 8Gbit through 64Gbit x4 and x8 3DS DDR3 SDRAM devices. This document was created based on the E revision of the DDR standard (JESD79). Each aspect of the changes for 3DS DDR3 SDRAM operation was considered. Committee(s): JC-42.3 Free download. Registration or login required. |