Standards & Documents Search

Displaying 61 - 120 of 159 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
Module Introduction	MODULE4	Oct 2001
Release No. 11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
General SDRAM Functions	SDRAM3.11.5.1	Jun 2002
Release No. 12 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
CONFIGURATIONS FOR SOLID STATE MEMORIES: Status: Under RevisionSections in this document may be under revision at any time.	JESD21-C	Jan 2003
This revision of JESD21 is substantially different from previous issues because it reflects advancement in semiconductor technology and computer design needs. A new class of memory devices, the multiport DRAM (MPDRAM) C also know as 'Video Ram' because of the most common application for the devices C is represented. A new family of SRAMs which addresses the increasing need for high speed is introduced. Additional families of devices in the SOJ and Zip packages are included. The material in this revision is organized primarily by function (ROM, EPROM, SRAM, DRAM, etc.) rather than by technology and word length. Pinouts for SIMM and DIMM are included along with presence detect schemes. A current set of terms has also been included. JESD21-C is a compilation of all memory device standards that have been developed by the JC-42 Committee and approved by the JEDEC BoD from September 1989 to present. This latest issue has changed to a loose-leaf format and comes in a three-ring binder so that new drawings can be added without requiring a new publication. Time of publication of the material is identified by release number, i.e., if marked Release 8, this item was approved and released in 1998, if marked Release 13, this item was approved and released in 2003. Committee(s): JC-42 See JESD21-C information
Byte Wide SRAM	SRAM3.7.5	Apr 2003
Release No.12 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex A, Table of Memory Types	SPD4.1.2.1	Apr 2003
Release No.12 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
4.5 Table of Contents - Eight Byte Modules	MODULE4.5	Apr 2003
Release No.12 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Device Specification Annex for JESD21-C	SDRAM3.2	Apr 2003
Release No.12 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex E, SDRAM	SPD4.1.2.5	May 2003
Release No. 12 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR Specific SDRAM Functions	SDRAM3.11.5.2	Jun 2003
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
COMMON FLASH INTERFACE (CFI):	JESD68.01	Sep 2003
The Common Flash Interface (CFI) specification outlines a device and host system software interrogation handshake that allows specific software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specific flash families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. The changes for this minor revision are indicated in Annex A on page 11. Committee(s): JC-42.4 Free download. Registration or login required.
144 Pin, PC133 SDRAM Unbuffered SO-DIMM, Reference Design Specification	MODULE4.20.3	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin, PC-133 SDRAM Registered DIMM Design Specification	MODULE4.20.2	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification	MODULE4.20.6	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DIMM Design Files	DIMM Homepage	Dec 2003
These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to downloading files. Design Files (Gerber Files) have been developed in accordance with the JEDEC Manual of Operation and Procedure. Committee(s): JC-42, JC-45 See DIMM Homepage information
Word Wide Graphics DRAM	MPDRAM3.10.3	Jan 2004
Release No.13 Committee(s): JC-42.3, JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Nibble Wide SDRAM	SDRAM3.11.2	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide SDRAM	SDRAM3.11.3	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex D, DDR Synchronous DRAM (DDR SDRAM)	SPD4.1.2.4	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
ANNUAL UPDATING SERVICE:	JESD21-C AUS	Jan 2004
The JEDEC Office has generated a mailing list for those who wish to subscribe to updates of this publication. A payment is required for subscription to this updating service. Committee(s): JC-42
COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODES:	JEP137B	May 2004
This publication is a companion document to the Common Flash Interface (CFI) standard, JESD68, which outlines the device and host system software interrogation handshake. JEP137 documents ID Code assignments for: 1)) the Algorithm-specific Command Set and Control Interfaces and 2) the Device Interfaces. It is published as needed when additions are made to either of these lists of codes. To make a request for an ID Code please contact the JEDEC Office at (703)907-7558. Committee(s): JC-42.4 Free download. Registration or login required.
100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification	MODULE4.20.9	Nov 2004
Release No. 14 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
EEPROM Extended Features	EEPROM3.5.3	Jan 2005
Release No.14 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
GDDR2 Specific SGRAM Functions	SDRAM3.11.5.6	May 2005
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
GDDR3 Specific SGRAM Functions	SDRAM3.11.5.7	May 2005
Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide EEPROM	EEPROM3.5.1	Aug 2005
Release No. 14 Committee(s): JC-42.4, JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SDRAM and SGRAM Architectural Operational Features Table of Contents	SDRAM3.11.5.TOC	May 2006
Release No.16 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex I, Serial Presence Detect for Virtual Channel SDRAM, Revision 2	SPD4.1.2.9	Jun 2006
Release No.9A Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION	JEP179	Jun 2006
The purpose of this document is to explain the meaning of SPD setting (JESD21 SPD section) for DDR2 SDRAM (JESD79-2) in normal and extended temperature operationy67. Committee(s): JC-42.3 Free download. Registration or login required.
SPD Annex J: Serial Presence Detect for DDR2 SDRAM	SPD4.1.2.10	Jan 2007
Release No. 17 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide TTL and MOS SRAM	SRAM3.7.7	Apr 2007
Release No. 16. Item 1541.03 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Double Word Wide MOS SRAM	SRAM3.7.8	Apr 2007
Release No. 16. Item 1541.03 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PSRAM, Pseudo-Static RAM	PSRAM3.8	Apr 2007
Release No. 16. Item 1633 Committee(s): JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
EEPROM, Word Wide	EEPROM3.5.2	Jun 2007
Release No. 16. Item 1704.1 Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Eight Byte Wide (X64/72) MOS SRAM	SRAM3.7.9	Jun 2007
Release No. 16A. Item 1480.05 and 1531.04 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPECIALITY DDR2-1066 SDRAM	JESD208	Nov 2007
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required.
High Speed DDR SRAM in 165 BGA	SRAM3.7.10	Feb 2008
Release No. 17. Item 1755 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide SDRAM.	SDRAM3.11.4	Feb 2008
Release No. 17. Item 1749.01 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DOUBLE DATA RATE (DDR) SDRAM STANDARD	JESD79F	Feb 2008
This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices. Committee(s): JC-42.3 Free download. Registration or login required.
JESD21C, Section 6, Applicable other documents for JESD21C	JESD21C.6	Mar 2008
Release No. 17 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR2 Specific SDRAM Function	SDRAM3.11.5.5	Jul 2008
Release No. 18 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Low Power Double Data Rate (LPDDR) Non-Volatile Memory (NVM) (Item 1674.17, 1674.16, 1674.20	NVRAM3.6.3	Feb 2009
Release No. 18A Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.	JESD209A-1	Mar 2009
This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices. Committee(s): JC-42.6 Free download. Registration or login required.
TSE2002 Serial Presence Detect with Thermal Sensor	PRN09-NV2	Jul 2009
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 1756.00A Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
TS3000 Standalone Thermal Sensor Component	SPD4.1.5	Nov 2009
Release No. 19A, Item 1640.11 Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR2 SDRAM STANDARD	JESD79-2F	Nov 2009
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD	JESD209B	Feb 2010
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Patents(): See Document Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required.
Serial Presence Detect (SPD) Table of Contents	SPD4.1.TOC	Mar 2010
Release No. 19 Committee(s): JC-42.3, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600	JESD79-3-2	Oct 2011
The purpose of this addendum is to define the DDR3U specifications that supersede the DDR3 specifications in the JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 titles in JESD79-3 are to be interpreted as DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600, respectively, when applying towards DDR3U definition; unless specifically stated otherwise. Item 1769.01 Committee(s): JC-42.3 Free download. Registration or login required.
WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)	JESD229	Dec 2011
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. Committee(s): JC-42, JC-42.6 Free download. Registration or login required.
DDR3 SDRAM STANDARD	JESD79-3F	Jul 2012
This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3 Available for purchase: $247.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 This is a minor editorial revision, the differences between revisions can be found on page 17 of the document.	JESD79-3-1A.01	May 2013
The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard. The purpose of this standard is to define the DDR3L specifications that supersede the DDR3 specifications as defined in JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, and DDR3L-1866 titles in JESD79-3 are to be interpreted as DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 respectively, when applying towards DDR3L definition; unless specifically stated otherwise. Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE 2 (LPDDR2)	JESD209-2F	Jun 2013
This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01G. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Free download. Registration or login required.
Addendum No. 3 to JESD79-3, 3D STACKED SDRAM	JESD79-3-3	Dec 2013
This addendum to JESD79-3 defines the 3DS DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for compliant 8Gbit through 64Gbit x4 and x8 3DS DDR3 SDRAM devices. This document was created based on the E revision of the DDR standard (JESD79). Each aspect of the changes for 3DS DDR3 SDRAM operation was considered. Committee(s): JC-42.3 Free download. Registration or login required.
GDDR5 MEASUREMENT PROCEDURES	JEP171	Aug 2014
This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5. Committee(s): JC-42.3 Free download. Registration or login required.
WIDE I/O 2 (WideIO2)	JESD229-2	Aug 2014
This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity. Committee(s): JC-42.6 Free download. Registration or login required.
Dual Inline Memory Modules (DIMMs) Table of Contents	MODULE4.20.TOC	Dec 2014
Release No. 24 Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)	JESD209-3C	Aug 2015
This document defines the LPDDR3 Standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Committee Item no. 1798.11D. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Available for purchase: $208.00 Add to Cart Paying JEDEC Members may login for free access.
LOW POWER DOUBLE DATA RATE 5 (LPDDR5) Status: Superseded JESD209-5A, January 2020	JESD209-5	Feb 2019
This document has been replaced by JESD209-5A. Members of JC-42.6 may access a reference copy on the restricted members' website. Committee(s): JC-42.6
Annex A: Differences between JESD21C Release 29 and its predecessor JESD21C, Release 28. Release Number: 29	AnnexA - JESD21C	Jan 2020
This table briefly describes the changes made to this standard, JESD21-C, Release 29, compared to its predecessor, JESD21C, Release 28. Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE (LPDDR5) Status: Superseded July 2021	JESD209-5A	Jan 2020
This document has been replaced by JESD209-5B. Item 1854.99A. Members of JC-42.6 may access a reference copy on the restricted members' website. Committee(s): JC-42.6

Standards & Documents Search

Module Introduction

General SDRAM Functions

CONFIGURATIONS FOR SOLID STATE MEMORIES:

Byte Wide SRAM

SPD Annex A, Table of Memory Types

4.5 Table of Contents - Eight Byte Modules

Device Specification Annex for JESD21-C

SPD Annex E, SDRAM

DDR Specific SDRAM Functions

COMMON FLASH INTERFACE (CFI):

144 Pin, PC133 SDRAM Unbuffered SO-DIMM, Reference Design Specification

168 Pin, PC-133 SDRAM Registered DIMM Design Specification

200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification

DIMM Design Files

Word Wide Graphics DRAM

Nibble Wide SDRAM

Byte Wide SDRAM

SPD Annex D, DDR Synchronous DRAM (DDR SDRAM)

ANNUAL UPDATING SERVICE:

COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODES:

100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification

EEPROM Extended Features

GDDR2 Specific SGRAM Functions

GDDR3 Specific SGRAM Functions

Byte Wide EEPROM

SDRAM and SGRAM Architectural Operational Features Table of Contents

SPD Annex I, Serial Presence Detect for Virtual Channel SDRAM, Revision 2

DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION

SPD Annex J: Serial Presence Detect for DDR2 SDRAM

Word Wide TTL and MOS SRAM

Double Word Wide MOS SRAM

PSRAM, Pseudo-Static RAM

EEPROM, Word Wide

Eight Byte Wide (X64/72) MOS SRAM

SPECIALITY DDR2-1066 SDRAM

High Speed DDR SRAM in 165 BGA

Word Wide SDRAM.

DOUBLE DATA RATE (DDR) SDRAM STANDARD

JESD21C, Section 6, Applicable other documents for JESD21C

DDR2 Specific SDRAM Function

Low Power Double Data Rate (LPDDR) Non-Volatile Memory (NVM) (Item 1674.17, 1674.16, 1674.20

Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.

TSE2002 Serial Presence Detect with Thermal Sensor

TS3000 Standalone Thermal Sensor Component

DDR2 SDRAM STANDARD

LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD

Serial Presence Detect (SPD) Table of Contents

Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600

WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)

DDR3 SDRAM STANDARD

Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866

LOW POWER DOUBLE DATA RATE 2 (LPDDR2)

Addendum No. 3 to JESD79-3, 3D STACKED SDRAM

GDDR5 MEASUREMENT PROCEDURES

WIDE I/O 2 (WideIO2)

Dual Inline Memory Modules (DIMMs) Table of Contents

LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)

LOW POWER DOUBLE DATA RATE 5 (LPDDR5)

Annex A: Differences between JESD21C Release 29 and its predecessor JESD21C, Release 28.

LOW POWER DOUBLE DATA RATE (LPDDR5)

Pages

Search by Keyword or Document Number

Filter by committees:

Filter by document type:

Filter by keywords: