Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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Word Wide TTL and MOS SRAM |
SRAM3.7.7 | Apr 2007 |
Release No. 16. Item 1541.03 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Word Wide SDRAM. |
SDRAM3.11.4 | Feb 2008 |
Release No. 17. Item 1749.01 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Word Wide ROM |
ROM3.2.2 | Dec 1992 |
Release No.6 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Word Wide PROM, DIP to SO Conversion |
PROM3.3.3-4 | Dec 1993 |
Release No.1 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Word Wide Graphics DRAM |
MPDRAM3.10.3 | Jan 2004 |
Release No.13 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Word Wide EPROM |
EPROM3.4.2 | Jun 1999 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Word Wide DRAM |
DRAM3.9.4 | Jul 2000 |
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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WIDE I/O SINGLE DATA RATE (WIDE I/O SDR) |
JESD229 | Dec 2011 |
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. Free download. Registration or login required. |
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WIDE I/O 2 (WideIO2) |
JESD229-2 | Aug 2014 |
This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity. Committee(s): JC-42.6 Free download. Registration or login required. |
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VCSDRAM Specific SDRAM Functions |
SDRAM3.11.5.4 | Jun 1999 |
Release No. 9 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Two Byte Modules Cards |
MODULE4.3 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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TSE2002 Serial Presence Detect with Thermal Sensor |
PRN09-NV2 | Jul 2009 |
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 1756.00A Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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TS3000 Standalone Thermal Sensor Component |
SPD4.1.5 | Nov 2009 |
Release No. 19A, Item 1640.11 Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SYSTEM LEVEL ROWHAMMER MITIGATION |
JEP301-1 | Mar 2021 |
A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02. Committee(s): JC-42 Free download. Registration or login required. |
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Synchronous Dynamic Random Access Memory (SDRAM) |
SDRAM3.11 | Jun 1994 |
Release No. 9 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Standard Template for JEDEC Module Standards |
MODULE4.20.1 | Oct 2001 |
Release No. 11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODE |
JEP106BK | Sep 2024 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Free download. Registration or login required. |
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STANDARD FOR 64K x 1 DYNAMIC RAM - SUPERSEDED BY JESD21-C.Status: RescindedApr-85 |
JEP102 | Jan 1978 |
Committee(s): JC-42 |
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SRAM Introduction |
SRAM3.7 | Oct 2001 |
Release No. 11 Committee(s): JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI) |
JESD255 | Mar 2024 |
The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus. Free download. Registration or login required. |
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SPECIALITY DDR2-1066 SDRAM |
JESD208 | Nov 2007 |
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required. |
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SPD Annex J: Serial Presence Detect for DDR2 SDRAM |
SPD4.1.2.10 | Jan 2007 |
Release No. 17 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex I, Serial Presence Detect for Virtual Channel SDRAM, Revision 2 |
SPD4.1.2.9 | Jun 2006 |
Release No.9A Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex H, ESDRAM Superset |
SPD4.1.2.8 | Jun 1999 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex F, Address Multiplexed ROM |
SPD4.1.2.6 | Jun 1998 |
Release No.8 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex E, SDRAM |
SPD4.1.2.5 | May 2003 |
Release No. 12 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex D, DDR Synchronous DRAM (DDR SDRAM) |
SPD4.1.2.4 | Jan 2004 |
Release No.13 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex C, Fast Page and Extended Data Out RAM |
SPD4.1.2.3 | Jan 1998 |
Release No.8 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex B, Table of Superset Memory Types |
SPD4.1.2.2 | Oct 2001 |
Release No.11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex A, Table of Memory Types |
SPD4.1.2.1 | Apr 2003 |
Release No.12 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Serial Presence Detect (SPD) Table of Contents |
SPD4.1.TOC | Mar 2010 |
Release No. 19 Committee(s): JC-42.3, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Serial NOR Security Hardware Abstraction Layer |
JESD261 | Nov 2022 |
This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device. Committee(s): JC-42.4 Free download. Registration or login required. |
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SERIAL FLASH RESET SIGNALING PROTOCOL |
JESD252.01 | Apr 2021 |
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06. Committee(s): JC-42.4 Free download. Registration or login required. |
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Serial Flash Discoverable Parameters (SFDP) |
JESD216G | Nov 2024 |
The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data. Committee(s): JC-42.4 Free download. Registration or login required. |
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Secure Serial Flash Bus TransactionsRelease Number: Version 1.0 |
JESD254 | Dec 2022 |
This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details about the secure transactions. This ballot does not describe the SFDP revisions or the secure packet structure. Patents(): Infineon- US 10868679B1 and Micron- US 9009394B2 Free download. Registration or login required. |
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SDRAM Parametric Standards |
SDRAM3.11.6 | Apr 1999 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SDRAM and SGRAM Architectural Operational Features Table of Contents |
SDRAM3.11.5.TOC | May 2006 |
Release No.16 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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PSRAM, Pseudo-Static RAM |
PSRAM3.8 | Apr 2007 |
Release No. 16. Item 1633 Committee(s): JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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PC-1600/PC-2100 DDR SDRAM Registered DIMM Design Specification (184 Pin) |
MODULE4.20.4 | May 2021 |
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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One Byte Modules |
MODULE4.2 | Jun 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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NVRAM, Nonvolatile RAM |
NVRAM3.6 | Dec 1991 |
Release No.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Nibble Wide SRAM |
SRAM3.7.3 | Dec 1995 |
Release No.5 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Nibble Wide SDRAM |
SDRAM3.11.2 | Jan 2004 |
Release No.13 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Nibble Wide PROM |
PROM3.3.1 | Dec 1993 |
Release No.1 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Nibble Wide MPDRAM |
MPDRAM3.10.1 | Jun 1997 |
Release No.9 Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Nibble Wide ECL SRAM |
SRAM3.7.4 | Dec 1994 |
Release No.04 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Nibble Wide DRAM |
DRAM3.9.2 | Jun 1999 |
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION |
JEP300-1 | Mar 2021 |
RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01. Committee(s): JC-42 Free download. Registration or login required. |
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NAND Flash Interface Interoperability |
JESD230G | Oct 2024 |
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Free download. Registration or login required. |
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MPDRAM Optional Features |
MPDRAM3.10.4 | Jun 1997 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Module Introduction |
MODULE4 | Oct 2001 |
Release No. 11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Mobile Platform Memory Module Thermal Sensor Component Specification |
MODULE4.7 | May 2022 |
Release No. 16. This replaces Release 15 and includes the following editorial changes: 1) Replaced master/slave with controller/target 2) Checked for presence of other sensitive words 3) Added Tables and Figures in Table of Contents (Release 15, Item 1640.07) Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Memory Module Nomenclature |
SPD4.1.1 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Low Power Double Data Rate Interface for Non-Volatile Memory (LPDDR4X-NVM) Standard |
JESD326-4 | Nov 2024 |
This standard defines the Low Power Double Data Rate interface for Non-Volatile Memory (LPDDR4XNVM) Standard. This standard describes features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit single channel LPDDR4X-NVM device. LPDDR4X-NVM density ranges from 128Mb through 32Gb. Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE 5 (LPDDR5)Status: Superseded JESD209-5A, January 2020 |
JESD209-5 | Feb 2019 |
This document has been replaced by JESD209-5A. Members of JC-42.6 may access a reference copy on the restricted members' website. Committee(s): JC-42.6 |
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Low Power Double Data Rate 4 (LPDDR4) |
JESD209-4E | Jun 2024 |
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb. Available for purchase: $374.00 Add to Cart Paying JEDEC Members may login for free access. |
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LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3) |
JESD209-3C | Aug 2015 |
This document defines the LPDDR3 Standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Committee Item no. 1798.11D. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Available for purchase: $208.00 Add to Cart Paying JEDEC Members may login for free access. |
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LOW POWER DOUBLE DATA RATE 2 (LPDDR2) |
JESD209-2F | Jun 2013 |
This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01G. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE (LPDDR5)Status: Superseded July 2021 |
JESD209-5A | Jan 2020 |
This document has been replaced by JESD209-5B. Item 1854.99A. Members of JC-42.6 may access a reference copy on the restricted members' website. Committee(s): JC-42.6 |
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LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD |
JESD209B | Feb 2010 |
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Patents(): See Document Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required. |