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Title	Document #	Date
REPLAY PROTECTED MONOTONIC COUNTER (RPMC) FOR SERIAL FLASH DEVICES	JESD260	Apr 2021
This document provides the requirements for an additional block called as Replay Protection Monotonic Counter. (RPMC) Replay Protection provides a building block towards providing additional security. This block requires modifications in both a Serial Flash device and Serial Flash Controller. The standard defines new commands for Replay Protected Monotonic Counter operations. A device that supports RPMC can support these new commands as defined in this standard. Committee(s): JC-42.4 Free download. Registration or login required.
Temperature Range and Measurement Standards for Components and Modules	JESD402-1B	Sep 2024
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Committee(s): JC-42 Free download. Registration or login required.
100 Pin DRAM, SDRAM, and ROM DIMM	MODULE4.4.8	Dec 1997
Release No. 8 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification	MODULE4.20.9	Nov 2004
Release No. 14 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
112 Pin MPDRAM DIMM	MODULE4.4.6	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin and 168 Pin PEMM Families with EDO-DRAM and SDRAM	MODULE4.5.13	Oct 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin DDR SGRAM SO-DIMM	MODULE4.5.9	Mar 1999
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin DRAM SO-DIMM	MODULE4.5.5	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin SDRAM SO-DIMM	MODULE4.5.6	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin SGRAM/SDRAM SO-DIMM Family	MODULE4.5.8	Oct 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin, PC133 SDRAM Unbuffered SO-DIMM, Reference Design Specification	MODULE4.20.3	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin DRAM DIMM	MODULE4.5.1	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin Registered SDRAM DIMM Family	MODULE4.5.7	Oct 2001
Release No.11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin Unbuffered DRAM DIMM	MODULE4.5.3	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin Unbuffered SDRAM DIMM	MODULE4.5.4	Jun 1999
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin, PC-133 SDRAM Registered DIMM Design Specification	MODULE4.20.2	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184 Pin DIMM Family Supplementary Design Standards	MODULE4.5.12	Oct 2000
Release No.10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184 Pin Unbuffered DDR SDRAM DIMM	MODULE4.5.10	May 2021
Release No.31 This revision contains terminology updates only. Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184 Pin Unbuffered SDR SDRAM DIMM Family	MODULE4.5.11	May 2021
Release No.31 This revision contains terminology updates only. Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184 Pin, PC-1600/PC-2100 DDR SDRAM Unbuffered DIMM Design Specification.	MODULE4.20.5	May 2021
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184-Pin PC-2700 SDRAM Unbuffered DIMM - TSOP-Based DRAMs Design Specification	MODULE4.20.8	May 2021
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
200 Pin SDRAM DIMM	MODULE4.5.2	Oct 2001
Release No.11 Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification	MODULE4.20.6	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
240-Pin Unbuffered and Registered DDR2 SDRAM DIMM Family	MODULE4.5.14	May 2021
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
278 Pin Buffered SDRAM DIMM	MODULE4.6.1	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
4.5 Table of Contents - Eight Byte Modules	MODULE4.5	Apr 2003
Release No.12 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
4.6 Table of Contents - Sixteen Byte Modules	MODULE4.6	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
64 & 72 Pin ZIP/SIMM SRAM Module	MODULE4.4.1	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
72 Pin DRAM SIMM	MODULE4.4.2	Dec 1997
Release No.8 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
72 Pin DRAM SO-DIMM	MODULE4.4.4	Jun 1997
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
80 Pin EEPROM SIMM	MODULE4.4.7	Dec 1997
Release No.8 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
88 Pin DRAM Card Status: Reaffirmed	MODULE4.4.3	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
88 Pin DRAM SO-DIMM	MODULE4.4.5	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)	JESD209-4-1A	Feb 2021
This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55A. Committee(s): JC-42.6 Available for purchase: $106.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.	JESD209A-1	Mar 2009
This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices. Committee(s): JC-42.6 Free download. Registration or login required.
Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE	JESD251-1.01	Sep 2021
This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus performance than legacy SPI memory implementations. Item 1775.15. This is an editorial revision to JESD251-1, October 2018 Committee(s): JC-42.4 Free download. Registration or login required.
Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 This is a minor editorial revision, the differences between revisions can be found on page 17 of the document.	JESD79-3-1A.01	May 2013
The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard. The purpose of this standard is to define the DDR3L specifications that supersede the DDR3 specifications as defined in JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, and DDR3L-1866 titles in JESD79-3 are to be interpreted as DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 respectively, when applying towards DDR3L definition; unless specifically stated otherwise. Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
Addendum No. 1 to JESD79-4, 3D STACKED DRAM	JESD79-4-1B	Feb 2021
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G Committee(s): JC-42.3C Free download. Registration or login required.
Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600	JESD79-3-2	Oct 2011
The purpose of this addendum is to define the DDR3U specifications that supersede the DDR3 specifications in the JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 titles in JESD79-3 are to be interpreted as DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600, respectively, when applying towards DDR3U definition; unless specifically stated otherwise. Item 1769.01 Committee(s): JC-42.3 Free download. Registration or login required.
Addendum No. 3 to JESD79-3, 3D STACKED SDRAM	JESD79-3-3	Dec 2013
This addendum to JESD79-3 defines the 3DS DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for compliant 8Gbit through 64Gbit x4 and x8 3DS DDR3 SDRAM devices. This document was created based on the E revision of the DDR standard (JESD79). Each aspect of the changes for 3DS DDR3 SDRAM operation was considered. Committee(s): JC-42.3 Free download. Registration or login required.
Annex A: Differences between JESD21C Release 29 and its predecessor JESD21C, Release 28. Release Number: 29	AnnexA - JESD21C	Jan 2020
This table briefly describes the changes made to this standard, JESD21-C, Release 29, compared to its predecessor, JESD21C, Release 28. Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
ANNUAL UPDATING SERVICE:	JESD21-C AUS	Jan 2004
The JEDEC Office has generated a mailing list for those who wish to subscribe to updates of this publication. A payment is required for subscription to this updating service. Committee(s): JC-42
Bit Wide DRAM	DRAM3.9.1	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Bit Wide ECL SRAM	SRAM3.7.2	Jul 1997
Release No. 9 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Bit Wide SDRAM	SDRAM3.11.1	Jun 1997
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Bit Wide TTL SRAM	SRAM3.7.1	Dec 1995
Release No. 5 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide	EPROM3.4.1	Jul 1997
Release No.9 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide DRAM	DRAM3.9.3	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide ECL SRAM	SRAM3.7.6	Jul 1997
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide EEPROM	EEPROM3.5.1	Aug 2005
Release No. 14 Committee(s): JC-42.4, JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide MPDRAM	MPDRAM3.10.2	Jun 1997
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide PROM	PROM3.3.2	Dec 1993
Release No.1 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide ROM	ROM3.2.1	Dec 1992
Release No.2 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide SDRAM	SDRAM3.11.3	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide SRAM	SRAM3.7.5	Apr 2003
Release No.12 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODES:	JEP137B	May 2004
This publication is a companion document to the Common Flash Interface (CFI) standard, JESD68, which outlines the device and host system software interrogation handshake. JEP137 documents ID Code assignments for: 1)) the Algorithm-specific Command Set and Control Interfaces and 2) the Device Interfaces. It is published as needed when additions are made to either of these lists of codes. To make a request for an ID Code please contact the JEDEC Office at (703)907-7558. Committee(s): JC-42.4 Free download. Registration or login required.
COMMON FLASH INTERFACE (CFI):	JESD68.01	Sep 2003
The Common Flash Interface (CFI) specification outlines a device and host system software interrogation handshake that allows specific software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specific flash families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. The changes for this minor revision are indicated in Annex A on page 11. Committee(s): JC-42.4 Free download. Registration or login required.
CONFIGURATIONS FOR SOLID STATE MEMORIES: Status: Under RevisionSections in this document may be under revision at any time.	JESD21-C	Jan 2003
This revision of JESD21 is substantially different from previous issues because it reflects advancement in semiconductor technology and computer design needs. A new class of memory devices, the multiport DRAM (MPDRAM) C also know as 'Video Ram' because of the most common application for the devices C is represented. A new family of SRAMs which addresses the increasing need for high speed is introduced. Additional families of devices in the SOJ and Zip packages are included. The material in this revision is organized primarily by function (ROM, EPROM, SRAM, DRAM, etc.) rather than by technology and word length. Pinouts for SIMM and DIMM are included along with presence detect schemes. A current set of terms has also been included. JESD21-C is a compilation of all memory device standards that have been developed by the JC-42 Committee and approved by the JEDEC BoD from September 1989 to present. This latest issue has changed to a loose-leaf format and comes in a three-ring binder so that new drawings can be added without requiring a new publication. Time of publication of the material is identified by release number, i.e., if marked Release 8, this item was approved and released in 1998, if marked Release 13, this item was approved and released in 2003. Committee(s): JC-42 See JESD21-C information
DDR Specific SDRAM Functions	SDRAM3.11.5.2	Jun 2003
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR2 SDRAM STANDARD	JESD79-2F	Nov 2009
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Committee(s): JC-42, JC-42.3 Free download. Registration or login required.

Standards & Documents Search

REPLAY PROTECTED MONOTONIC COUNTER (RPMC) FOR SERIAL FLASH DEVICES

Temperature Range and Measurement Standards for Components and Modules

100 Pin DRAM, SDRAM, and ROM DIMM

100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification

112 Pin MPDRAM DIMM

144 Pin and 168 Pin PEMM Families with EDO-DRAM and SDRAM

144 Pin DDR SGRAM SO-DIMM

144 Pin DRAM SO-DIMM

144 Pin SDRAM SO-DIMM

144 Pin SGRAM/SDRAM SO-DIMM Family

144 Pin, PC133 SDRAM Unbuffered SO-DIMM, Reference Design Specification

168 Pin DRAM DIMM

168 Pin Registered SDRAM DIMM Family

168 Pin Unbuffered DRAM DIMM

168 Pin Unbuffered SDRAM DIMM

168 Pin, PC-133 SDRAM Registered DIMM Design Specification

184 Pin DIMM Family Supplementary Design Standards

184 Pin Unbuffered DDR SDRAM DIMM

184 Pin Unbuffered SDR SDRAM DIMM Family

184 Pin, PC-1600/PC-2100 DDR SDRAM Unbuffered DIMM Design Specification.

184-Pin PC-2700 SDRAM Unbuffered DIMM - TSOP-Based DRAMs Design Specification

200 Pin SDRAM DIMM

200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification

240-Pin Unbuffered and Registered DDR2 SDRAM DIMM Family

278 Pin Buffered SDRAM DIMM

4.5 Table of Contents - Eight Byte Modules

4.6 Table of Contents - Sixteen Byte Modules

64 & 72 Pin ZIP/SIMM SRAM Module

72 Pin DRAM SIMM

72 Pin DRAM SO-DIMM

80 Pin EEPROM SIMM

88 Pin DRAM Card

88 Pin DRAM SO-DIMM

ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)

Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.

Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE

Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866

Addendum No. 1 to JESD79-4, 3D STACKED DRAM

Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600

Addendum No. 3 to JESD79-3, 3D STACKED SDRAM

Annex A: Differences between JESD21C Release 29 and its predecessor JESD21C, Release 28.

ANNUAL UPDATING SERVICE:

Bit Wide DRAM

Bit Wide ECL SRAM

Bit Wide SDRAM

Bit Wide TTL SRAM

Byte Wide

Byte Wide DRAM

Byte Wide ECL SRAM

Byte Wide EEPROM

Byte Wide MPDRAM

Byte Wide PROM

Byte Wide ROM

Byte Wide SDRAM

Byte Wide SRAM

COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODES:

COMMON FLASH INTERFACE (CFI):

CONFIGURATIONS FOR SOLID STATE MEMORIES:

DDR Specific SDRAM Functions

DDR2 SDRAM STANDARD

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