Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
Addendum No. 1 to JESD79-4, 3D STACKED DRAM |
JESD79-4-1B | Feb 2021 |
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G Committee(s): JC-42.3C Free download. Registration or login required. |
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ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X) |
JESD209-4-1A | Feb 2021 |
This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55A. Committee(s): JC-42.6 Available for purchase: $106.00 Add to Cart Paying JEDEC Members may login for free access. |
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DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD |
JESD404-1 | Nov 2020 |
Definition for all DDRx component documents to reference. This is generic to any DDRx Committee(s): JC-42.3C Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE (LPDDR5)Status: Superseded July 2021 |
JESD209-5A | Jan 2020 |
This document has been replaced by JESD209-5B. Item 1854.99A. Members of JC-42.6 may access a reference copy on the restricted members' website. Committee(s): JC-42.6 |
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Annex A: Differences between JESD21C Release 29 and its predecessor JESD21C, Release 28.Release Number: 29 |
AnnexA - JESD21C | Jan 2020 |
This table briefly describes the changes made to this standard, JESD21-C, Release 29, compared to its predecessor, JESD21C, Release 28. Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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