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Title	Document #	Date
Serial Flash Discoverable Parameters (SFDP)	JESD216G	Nov 2024
The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data. Committee(s): JC-42.4 Free download. Registration or login required.
STANDARD MANUFACTURER'S IDENTIFICATION CODE	JEP106BL	Feb 2025
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
Graphics Double Data Rate 7 SGRAM Standard (GDDR7)	JESD239B	Feb 2025
This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. Committee(s): JC-42, JC-42.1 Free download. Registration or login required.
High Bandwidth Memory (HBM3) DRAM	JESD238B.01	Apr 2025
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42, JC-42.2 Free download. Registration or login required.
High Bandwidth Memory (HBM4) DRAM	JESD270-4	Apr 2025
The HBM4 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM4 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). The JESD271-4 HBM4 Bump Matrix Spreadsheet will be available in early May. Patents(): There are several patent notifications claims in the JEDEC patent letter spreadsheet file for HBM. I do not know if any of these are going to be asserted against this HBM4 specification but this list is included in the BoD ballot content for reference. Committee(s): JC-42, JC-42.2 Free download. Registration or login required.

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