Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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Dual Inline Memory Modules (DIMMs) Table of Contents |
MODULE4.20.TOC | Dec 2014 |
Release No. 24 Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR4 SDRAM STANDARD |
JESD79-4D | Jul 2021 |
This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78H Committee(s): JC-42.3C Available for purchase: $284.00 Add to Cart Paying JEDEC Members may login for free access. |
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LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD |
JESD209B | Feb 2010 |
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Patents(): See Document Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE 2 (LPDDR2) |
JESD209-2F | Jun 2013 |
This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01G. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Free download. Registration or login required. |
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DDR3 SDRAM STANDARD |
JESD79-3F | Jul 2012 |
This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3 Available for purchase: $247.00 Add to Cart Paying JEDEC Members may login for free access. |
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TS3000 Standalone Thermal Sensor Component |
SPD4.1.5 | Nov 2009 |
Release No. 19A, Item 1640.11 Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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HIGH BANDWIDTH MEMORY (HBM) DRAM |
JESD235D | Mar 2021 |
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L. Committee(s): JC-42.3C Available for purchase: $247.00 Add to Cart Paying JEDEC Members may login for free access. |
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GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARDRelease Number: C.01 - Terminology update |
JESD212C.01 | Jan 2023 |
Terminology update. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3C Free download. Registration or login required. |
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JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES |
JEP166E | Jul 2023 |
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories Committee(s): JC-42.6 Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3) |
JESD209-3C | Aug 2015 |
This document defines the LPDDR3 Standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Committee Item no. 1798.11D. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Available for purchase: $208.00 Add to Cart Paying JEDEC Members may login for free access. |
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DDR2 SDRAM STANDARD |
JESD79-2F | Nov 2009 |
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Free download. Registration or login required. |
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Low Power Double Data Rate 4 (LPDDR4) |
JESD209-4E | Jun 2024 |
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb. Available for purchase: $374.00 Add to Cart Paying JEDEC Members may login for free access. |
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Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866This is a minor editorial revision, the differences between revisions can be found on page 17 of the document. |
JESD79-3-1A.01 | May 2013 |
The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard. The purpose of this standard is to define the DDR3L specifications that supersede the DDR3 specifications as defined in JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, and DDR3L-1866 titles in JESD79-3 are to be interpreted as DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 respectively, when applying towards DDR3L definition; unless specifically stated otherwise. Free download. Registration or login required. |
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Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications |
SPD4.1.6-01 | May 2022 |
Release 26.01, Terminology update This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROM (EE) and Temperature Sensor (TS) as used for memory module applications. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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PC-1600/PC-2100 DDR SDRAM Registered DIMM Design Specification (184 Pin) |
MODULE4.20.4 | May 2021 |
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD |
JESD232A.01 | Mar 2023 |
Terminology update. This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package Committee(s): JC-42.3, JC-42.3C Free download. Registration or login required. |
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Addendum No. 3 to JESD79-3, 3D STACKED SDRAM |
JESD79-3-3 | Dec 2013 |
This addendum to JESD79-3 defines the 3DS DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for compliant 8Gbit through 64Gbit x4 and x8 3DS DDR3 SDRAM devices. This document was created based on the E revision of the DDR standard (JESD79). Each aspect of the changes for 3DS DDR3 SDRAM operation was considered. Committee(s): JC-42.3 Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODE |
JEP106BK | Sep 2024 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Free download. Registration or login required. |
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Addendum No. 1 to JESD79-4, 3D STACKED DRAM |
JESD79-4-1B | Feb 2021 |
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G Committee(s): JC-42.3C Free download. Registration or login required. |
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ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X) |
JESD209-4-1A | Feb 2021 |
This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55A. Committee(s): JC-42.6 Available for purchase: $106.00 Add to Cart Paying JEDEC Members may login for free access. |
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Graphics Double Data Rate (GDDR6) SGRAM Standard |
JESD250D | May 2023 |
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s): JC-42.3C Free download. Registration or login required. |
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EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES |
JESD251C | May 2022 |
This standard specifies the eXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, which provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is primarily for use in computing, automotive, Internet Of Things (IOT), embedded systems and mobile systems, between host processing and peripheral devices. The xSPI electrical interface can deliver up to 400 MBytes per second raw data throughput. Item 1775.74. Committee(s): JC-42.4 Free download. Registration or login required. |
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Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE |
JESD251-1.01 | Sep 2021 |
This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus performance than legacy SPI memory implementations. Item 1775.15. This is an editorial revision to JESD251-1, October 2018 Committee(s): JC-42.4 Free download. Registration or login required. |
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SERIAL FLASH RESET SIGNALING PROTOCOL |
JESD252.01 | Apr 2021 |
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06. Committee(s): JC-42.4 Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE 5 (LPDDR5)Status: Superseded JESD209-5A, January 2020 |
JESD209-5 | Feb 2019 |
This document has been replaced by JESD209-5A. Members of JC-42.6 may access a reference copy on the restricted members' website. Committee(s): JC-42.6 |
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LOW POWER DOUBLE DATA RATE (LPDDR5)Status: Superseded July 2021 |
JESD209-5A | Jan 2020 |
This document has been replaced by JESD209-5B. Item 1854.99A. Members of JC-42.6 may access a reference copy on the restricted members' website. Committee(s): JC-42.6 |
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DDR5 SDRAMRelease Number: Version 1.31 |
JESD79-5C.01 | Jul 2024 |
Version 1.31 This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4). Available for purchase: $423.00 Add to Cart Paying JEDEC Members may login for free access. |
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Temperature Range and Measurement Standards for Components and Modules |
JESD402-1B | Sep 2024 |
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Committee(s): JC-42 Free download. Registration or login required. |
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DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD |
JESD404-1 | Nov 2020 |
Definition for all DDRx component documents to reference. This is generic to any DDRx Committee(s): JC-42.3C Free download. Registration or login required. |
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NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION |
JEP300-1 | Mar 2021 |
RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01. Committee(s): JC-42 Free download. Registration or login required. |
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SYSTEM LEVEL ROWHAMMER MITIGATION |
JEP301-1 | Mar 2021 |
A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02. Committee(s): JC-42 Free download. Registration or login required. |
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REPLAY PROTECTED MONOTONIC COUNTER (RPMC) FOR SERIAL FLASH DEVICES |
JESD260 | Apr 2021 |
This document provides the requirements for an additional block called as Replay Protection Monotonic Counter. (RPMC) Replay Protection provides a building block towards providing additional security. This block requires modifications in both a Serial Flash device and Serial Flash Controller. The standard defines new commands for Replay Protected Monotonic Counter operations. A device that supports RPMC can support these new commands as defined in this standard. Committee(s): JC-42.4 Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X |
JESD209-5C | Jul 2023 |
This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4). Available for purchase: $459.00 Add to Cart Paying JEDEC Members may login for free access. |
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HIGH BANDWIDTH MEMORY (HBM3) DRAM |
JESD238A | Jan 2023 |
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Free download. Registration or login required. |
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Serial NOR Security Hardware Abstraction Layer |
JESD261 | Nov 2022 |
This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device. Committee(s): JC-42.4 Free download. Registration or login required. |
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Secure Serial Flash Bus TransactionsRelease Number: Version 1.0 |
JESD254 | Dec 2022 |
This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details about the secure transactions. This ballot does not describe the SFDP revisions or the secure packet structure. Patents(): Infineon- US 10868679B1 and Micron- US 9009394B2 Free download. Registration or login required. |
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Graphics Double Data Rate 7 SGRAM Standard (GDDR7) |
JESD239A | Sep 2024 |
This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.
Free download. Registration or login required. |
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SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI) |
JESD255 | Mar 2024 |
The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus. Free download. Registration or login required. |
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