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Title	Document #	Date
GDDR3 Specific SGRAM Functions	SDRAM3.11.5.7	May 2005
Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
General SDRAM Functions	SDRAM3.11.5.1	Jun 2002
Release No. 12 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR2 Specific SDRAM Function	SDRAM3.11.5.5	Jul 2008
Release No. 18 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
VCSDRAM Specific SDRAM Functions	SDRAM3.11.5.4	Jun 1999
Release No. 9 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Low Power Double Data Rate (LPDDR) Non-Volatile Memory (NVM) (Item 1674.17, 1674.16, 1674.20	NVRAM3.6.3	Feb 2009
Release No. 18A Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR Specific SDRAM Functions	SDRAM3.11.5.2	Jun 2003
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Enhanced SDRAM (ESDRAM) Specific SDRAM Functions	SDRAM3.11.5.3	Jun 1999
Release No. 9 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Mobile Platform Memory Module Thermal Sensor Component Specification	MODULE4.7	May 2022
Release No. 16. This replaces Release 15 and includes the following editorial changes: 1) Replaced master/slave with controller/target 2) Checked for presence of other sensitive words 3) Added Tables and Figures in Table of Contents (Release 15, Item 1640.07) Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION	JEP179	Jun 2006
The purpose of this document is to explain the meaning of SPD setting (JESD21 SPD section) for DDR2 SDRAM (JESD79-2) in normal and extended temperature operationy67. Committee(s): JC-42.3 Free download. Registration or login required.
Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.	JESD209A-1	Mar 2009
This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices. Committee(s): JC-42.6 Free download. Registration or login required.
JESD21C, Section 6, Applicable other documents for JESD21C	JESD21C.6	Mar 2008
Release No. 17 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
STANDARD FOR 64K x 1 DYNAMIC RAM - SUPERSEDED BY JESD21-C. Status: RescindedApr-85	JEP102	Jan 1978
Committee(s): JC-42
ANNUAL UPDATING SERVICE:	JESD21-C AUS	Jan 2004
The JEDEC Office has generated a mailing list for those who wish to subscribe to updates of this publication. A payment is required for subscription to this updating service. Committee(s): JC-42
Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs	SPD4.1.3-01	May 2022
Release No. 19.01. Item 1739.02E, Terminology update. This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROMs as used for memory module applications. Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
CONFIGURATIONS FOR SOLID STATE MEMORIES: Status: Under RevisionSections in this document may be under revision at any time.	JESD21-C	Jan 2003
This revision of JESD21 is substantially different from previous issues because it reflects advancement in semiconductor technology and computer design needs. A new class of memory devices, the multiport DRAM (MPDRAM) C also know as 'Video Ram' because of the most common application for the devices C is represented. A new family of SRAMs which addresses the increasing need for high speed is introduced. Additional families of devices in the SOJ and Zip packages are included. The material in this revision is organized primarily by function (ROM, EPROM, SRAM, DRAM, etc.) rather than by technology and word length. Pinouts for SIMM and DIMM are included along with presence detect schemes. A current set of terms has also been included. JESD21-C is a compilation of all memory device standards that have been developed by the JC-42 Committee and approved by the JEDEC BoD from September 1989 to present. This latest issue has changed to a loose-leaf format and comes in a three-ring binder so that new drawings can be added without requiring a new publication. Time of publication of the material is identified by release number, i.e., if marked Release 8, this item was approved and released in 1998, if marked Release 13, this item was approved and released in 2003. Committee(s): JC-42 See JESD21-C information
Graphics Double Data (GDDR4) SGRAM Standard Release Number: 16	SDRAM3.11.5.8 R16.01	Mar 2023
Item 1600.41, Terminology Update This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics Random Access Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices. Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
100 Pin DRAM, SDRAM, and ROM DIMM	MODULE4.4.8	Dec 1997
Release No. 8 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Serial Presence Detect (SPD) Table of Contents	SPD4.1.TOC	Mar 2010
Release No. 19 Committee(s): JC-42.3, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
EEPROM, Word Wide	EEPROM3.5.2	Jun 2007
Release No. 16. Item 1704.1 Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Eight Byte Wide (X64/72) MOS SRAM	SRAM3.7.9	Jun 2007
Release No. 16A. Item 1480.05 and 1531.04 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide TTL and MOS SRAM	SRAM3.7.7	Apr 2007
Release No. 16. Item 1541.03 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Double Word Wide MOS SRAM	SRAM3.7.8	Apr 2007
Release No. 16. Item 1541.03 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PSRAM, Pseudo-Static RAM	PSRAM3.8	Apr 2007
Release No. 16. Item 1633 Committee(s): JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin, PC-133 SDRAM Registered DIMM Design Specification	MODULE4.20.2	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification	MODULE4.20.6	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184-Pin PC-2700 SDRAM Unbuffered DIMM - TSOP-Based DRAMs Design Specification	MODULE4.20.8	May 2021
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184 Pin, PC-1600/PC-2100 DDR SDRAM Unbuffered DIMM Design Specification.	MODULE4.20.5	May 2021
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPECIALITY DDR2-1066 SDRAM	JESD208	Nov 2007
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required.
SPD Annex J: Serial Presence Detect for DDR2 SDRAM	SPD4.1.2.10	Jan 2007
Release No. 17 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications	SPD4.1.4-01	May 2022
Release No. 21.01, Terminology update. This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROMs and Temperature Sensor (TS) as used for memory module applications. The designation TSE2002av refers to the family of devices specified by this document. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600	JESD79-3-2	Oct 2011
The purpose of this addendum is to define the DDR3U specifications that supersede the DDR3 specifications in the JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 titles in JESD79-3 are to be interpreted as DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600, respectively, when applying towards DDR3U definition; unless specifically stated otherwise. Item 1769.01 Committee(s): JC-42.3 Free download. Registration or login required.
DIMM Design Files	DIMM Homepage	Dec 2003
These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to downloading files. Design Files (Gerber Files) have been developed in accordance with the JEDEC Manual of Operation and Procedure. Committee(s): JC-42, JC-45 See DIMM Homepage information
DOUBLE DATA RATE (DDR) SDRAM STANDARD	JESD79F	Feb 2008
This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices. Committee(s): JC-42.3 Free download. Registration or login required.
WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)	JESD229	Dec 2011
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. Committee(s): JC-42, JC-42.6 Free download. Registration or login required.
NAND Flash Interface Interoperability	JESD230G	Oct 2024
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP) This document replaces JESD216F.01, Editorial changes to this document were approved by the TG, June 2022	JESD216F.02	Jun 2022
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office at juliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.73. Editorial changes listed in Annex, from original publication of JESD216F (December 2021). Committee(s): JC-42.4 Free download. Registration or login required.
GDDR5 MEASUREMENT PROCEDURES	JEP171	Aug 2014
This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5. Committee(s): JC-42.3 Free download. Registration or login required.
WIDE I/O 2 (WideIO2)	JESD229-2	Aug 2014
This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity. Committee(s): JC-42.6 Free download. Registration or login required.
SDRAM and SGRAM Architectural Operational Features Table of Contents	SDRAM3.11.5.TOC	May 2006
Release No.16 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex A: Differences between JESD21C Release 29 and its predecessor JESD21C, Release 28. Release Number: 29	AnnexA - JESD21C	Jan 2020
This table briefly describes the changes made to this standard, JESD21-C, Release 29, compared to its predecessor, JESD21C, Release 28. Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

Standards & Documents Search

GDDR3 Specific SGRAM Functions

General SDRAM Functions

DDR2 Specific SDRAM Function

VCSDRAM Specific SDRAM Functions

Low Power Double Data Rate (LPDDR) Non-Volatile Memory (NVM) (Item 1674.17, 1674.16, 1674.20

DDR Specific SDRAM Functions

Enhanced SDRAM (ESDRAM) Specific SDRAM Functions

Mobile Platform Memory Module Thermal Sensor Component Specification

DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION

Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.

JESD21C, Section 6, Applicable other documents for JESD21C

STANDARD FOR 64K x 1 DYNAMIC RAM - SUPERSEDED BY JESD21-C.

ANNUAL UPDATING SERVICE:

Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs

CONFIGURATIONS FOR SOLID STATE MEMORIES:

Graphics Double Data (GDDR4) SGRAM Standard

100 Pin DRAM, SDRAM, and ROM DIMM

Serial Presence Detect (SPD) Table of Contents

EEPROM, Word Wide

Eight Byte Wide (X64/72) MOS SRAM

Word Wide TTL and MOS SRAM

Double Word Wide MOS SRAM

PSRAM, Pseudo-Static RAM

168 Pin, PC-133 SDRAM Registered DIMM Design Specification

200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification

184-Pin PC-2700 SDRAM Unbuffered DIMM - TSOP-Based DRAMs Design Specification

184 Pin, PC-1600/PC-2100 DDR SDRAM Unbuffered DIMM Design Specification.

SPECIALITY DDR2-1066 SDRAM

SPD Annex J: Serial Presence Detect for DDR2 SDRAM

Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications

Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600

DIMM Design Files

DOUBLE DATA RATE (DDR) SDRAM STANDARD

WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)

NAND Flash Interface Interoperability

SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)

GDDR5 MEASUREMENT PROCEDURES

WIDE I/O 2 (WideIO2)

SDRAM and SGRAM Architectural Operational Features Table of Contents

Annex A: Differences between JESD21C Release 29 and its predecessor JESD21C, Release 28.

Pages

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