Standards & Documents Search

Displaying 1 - 20 of 159 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
Word Wide TTL and MOS SRAM	SRAM3.7.7	Apr 2007
Release No. 16. Item 1541.03 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide SDRAM.	SDRAM3.11.4	Feb 2008
Release No. 17. Item 1749.01 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide ROM	ROM3.2.2	Dec 1992
Release No.6 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide PROM, DIP to SO Conversion	PROM3.3.3-4	Dec 1993
Release No.1 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide Graphics DRAM	MPDRAM3.10.3	Jan 2004
Release No.13 Committee(s): JC-42.3, JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide EPROM	EPROM3.4.2	Jun 1999
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide DRAM	DRAM3.9.4	Jul 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)	JESD229	Dec 2011
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. Committee(s): JC-42, JC-42.6 Free download. Registration or login required.
WIDE I/O 2 (WideIO2)	JESD229-2	Aug 2014
This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity. Committee(s): JC-42.6 Free download. Registration or login required.
VCSDRAM Specific SDRAM Functions	SDRAM3.11.5.4	Jun 1999
Release No. 9 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Two Byte Modules Cards	MODULE4.3	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
TSE2002 Serial Presence Detect with Thermal Sensor	PRN09-NV2	Jul 2009
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 1756.00A Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
TS3000 Standalone Thermal Sensor Component	SPD4.1.5	Nov 2009
Release No. 19A, Item 1640.11 Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SYSTEM LEVEL ROWHAMMER MITIGATION	JEP301-1	Mar 2021
A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02. Committee(s): JC-42 Free download. Registration or login required.
Synchronous Dynamic Random Access Memory (SDRAM)	SDRAM3.11	Jun 1994
Release No. 9 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Standard Template for JEDEC Module Standards	MODULE4.20.1	Oct 2001
Release No. 11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
STANDARD MANUFACTURERS IDENTIFICATION CODE	JEP106BK	Sep 2024
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
STANDARD FOR 64K x 1 DYNAMIC RAM - SUPERSEDED BY JESD21-C. Status: RescindedApr-85	JEP102	Jan 1978
Committee(s): JC-42
SRAM Introduction	SRAM3.7	Oct 2001
Release No. 11 Committee(s): JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)	JESD255	Mar 2024
The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.

Standards & Documents Search

Word Wide TTL and MOS SRAM

Word Wide SDRAM.

Word Wide ROM

Word Wide PROM, DIP to SO Conversion

Word Wide Graphics DRAM

Word Wide EPROM

Word Wide DRAM

WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)

WIDE I/O 2 (WideIO2)

VCSDRAM Specific SDRAM Functions

Two Byte Modules Cards

TSE2002 Serial Presence Detect with Thermal Sensor

TS3000 Standalone Thermal Sensor Component

SYSTEM LEVEL ROWHAMMER MITIGATION

Synchronous Dynamic Random Access Memory (SDRAM)

Standard Template for JEDEC Module Standards

STANDARD MANUFACTURERS IDENTIFICATION CODE

STANDARD FOR 64K x 1 DYNAMIC RAM - SUPERSEDED BY JESD21-C.

SRAM Introduction

SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)

Pages

Search by Keyword or Document Number

Filter by committees:

Filter by document type:

Filter by keywords: