Standards & Documents Search

This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01G.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-42.6

Free download. Registration or login required.

This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb.

Committee(s): JC-42, JC-42.6

Available for purchase: $374.00 Add to Cart

Paying JEDEC Members may login for free access.

This standard defines the Low Power Double Data Rate interface for Non-Volatile Memory (LPDDR4XNVM) Standard. This standard describes features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements

for a JEDEC compliant 16 bit single channel LPDDR4X-NVM device. LPDDR4X-NVM density ranges from 128Mb through 32Gb.

Committee(s): JC-42, JC-42.6

Free download. Registration or login required.

Release No. 16.

This replaces Release 15 and includes the following editorial changes: 1) Replaced master/slave with controller/target 2) Checked for presence of other sensitive words 3) Added Tables and Figures in Table of Contents

(Release 15, Item 1640.07)

Committee(s): JC-42.4

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No.9

Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01.

Committee(s): JC-42

Free download. Registration or login required.

Release No.04

Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No.1

Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No.5

Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.