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Title	Document #	Date
PC-1600/PC-2100 DDR SDRAM Registered DIMM Design Specification (184 Pin)	MODULE4.20.4	May 2021
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PSRAM, Pseudo-Static RAM	PSRAM3.8	Apr 2007
Release No. 16. Item 1633 Committee(s): JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SDRAM and SGRAM Architectural Operational Features Table of Contents	SDRAM3.11.5.TOC	May 2006
Release No.16 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SDRAM Parametric Standards	SDRAM3.11.6	Apr 1999
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Secure Serial Flash Bus Transactions Release Number: Version 1.0	JESD254	Dec 2022
This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details about the secure transactions. This ballot does not describe the SFDP revisions or the secure packet structure. Patents(): Infineon- US 10868679B1 and Micron- US 9009394B2 Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
Serial Flash Discoverable Parameters (SFDP)	JESD216G	Nov 2024
The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data. Committee(s): JC-42.4 Free download. Registration or login required.
SERIAL FLASH RESET SIGNALING PROTOCOL	JESD252.01	Apr 2021
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06. Committee(s): JC-42.4 Free download. Registration or login required.
Serial NOR Security Hardware Abstraction Layer	JESD261	Nov 2022
This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device. Committee(s): JC-42.4 Free download. Registration or login required.
Serial Presence Detect (SPD) Table of Contents	SPD4.1.TOC	Mar 2010
Release No. 19 Committee(s): JC-42.3, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex A, Table of Memory Types	SPD4.1.2.1	Apr 2003
Release No.12 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex B, Table of Superset Memory Types	SPD4.1.2.2	Oct 2001
Release No.11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex C, Fast Page and Extended Data Out RAM	SPD4.1.2.3	Jan 1998
Release No.8 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex D, DDR Synchronous DRAM (DDR SDRAM)	SPD4.1.2.4	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex E, SDRAM	SPD4.1.2.5	May 2003
Release No. 12 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex F, Address Multiplexed ROM	SPD4.1.2.6	Jun 1998
Release No.8 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex H, ESDRAM Superset	SPD4.1.2.8	Jun 1999
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex I, Serial Presence Detect for Virtual Channel SDRAM, Revision 2	SPD4.1.2.9	Jun 2006
Release No.9A Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex J: Serial Presence Detect for DDR2 SDRAM	SPD4.1.2.10	Jan 2007
Release No. 17 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPECIALITY DDR2-1066 SDRAM	JESD208	Nov 2007
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required.
SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)	JESD255	Mar 2024
The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.

Standards & Documents Search

PC-1600/PC-2100 DDR SDRAM Registered DIMM Design Specification (184 Pin)

PSRAM, Pseudo-Static RAM

SDRAM and SGRAM Architectural Operational Features Table of Contents

SDRAM Parametric Standards

Secure Serial Flash Bus Transactions

Serial Flash Discoverable Parameters (SFDP)

SERIAL FLASH RESET SIGNALING PROTOCOL

Serial NOR Security Hardware Abstraction Layer

Serial Presence Detect (SPD) Table of Contents

SPD Annex A, Table of Memory Types

SPD Annex B, Table of Superset Memory Types

SPD Annex C, Fast Page and Extended Data Out RAM

SPD Annex D, DDR Synchronous DRAM (DDR SDRAM)

SPD Annex E, SDRAM

SPD Annex F, Address Multiplexed ROM

SPD Annex H, ESDRAM Superset

SPD Annex I, Serial Presence Detect for Virtual Channel SDRAM, Revision 2

SPD Annex J: Serial Presence Detect for DDR2 SDRAM

SPECIALITY DDR2-1066 SDRAM

SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)

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