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This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007).

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Committee(s): JC-42.3, JC-42.6

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This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14

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Committee(s): JC-42.3

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The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L.

Committee(s): JC-42.3C

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This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories

Committee(s): JC-42.6

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This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01

Committee(s): JC-42, JC-42.3

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The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard. The purpose of this standard is to define the DDR3L specifications that supersede the DDR3 specifications as defined in JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, and DDR3L-1866 titles in JESD79-3 are to be interpreted as DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 respectively, when applying towards DDR3L definition; unless specifically stated otherwise.

Committee(s): JC-42, JC-42.3

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Release No. 31

This revision contains terminology updates only.

Committee(s): JC-42.5

JESD21-C Solid State Memory Documents Main Page

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This addendum to JESD79-3 defines the 3DS DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for compliant 8Gbit through 64Gbit x4 and x8 3DS DDR3 SDRAM devices. This document was created based on the E revision of the DDR standard (JESD79). Each aspect of the changes for 3DS DDR3 SDRAM operation was considered.

Committee(s): JC-42.3

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This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G

Committee(s): JC-42.3C

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