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Title	Document #	Date
Graphics Double Data Rate (GDDR6) SGRAM Standard	JESD250D	May 2023
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s): JC-42.3C Free download. Registration or login required.
NAND Flash Interface Interoperability	JESD230F.01	May 2023
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s): JC-42.4 Free download. Registration or login required.
STANDARD MANUFACTURERS IDENTIFICATION CODE NOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded.	JEP106BG	May 2023
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
Graphics Double Data (GDDR4) SGRAM Standard Release Number: 16	SDRAM3.11.5.8 R16.01	Mar 2023
Item 1600.41, Terminology Update This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics RandomAccess Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices. Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD	JESD232A.01	Mar 2023
Terminology update. This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package Committee(s): JC-42.3, JC-42.3C Free download. Registration or login required.
GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD Release Number: C.01 - Terminology update	JESD212C.01	Jan 2023
Terminology update. This document defines the Graphics Double Data Rate 5 (GDDR5) Synchronous Graphics Random Access Memory (SGRAM), including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC standard compatible 512 Mb through 8 Gb x32 GDDR5 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR5 SGRAM vendors providing JEDEC standard compatible devices. Some aspects of the GDDR5 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. Item 1733.70B Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3C Free download. Registration or login required.
HIGH BANDWIDTH MEMORY (HBM3) DRAM	JESD238A	Jan 2023
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42, JC-42.2 Free download. Registration or login required.
Secure Serial Flash Bus Transactions Release Number: Version 1.0	JESD254	Dec 2022
This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details about the secure transactions. This ballot does not describe the SFDP revisions or the secure packet structure. Patents(): Infineon- US 10868679B1 and Micron- US 9009394B2 Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
Serial NOR Security Hardware Abstraction Layer	JESD261	Nov 2022
This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device. Committee(s): JC-42.4 Free download. Registration or login required.
DDR5 SDRAM Release Number: Version 1.2	JESD79-5B	Aug 2022
This standard defines the DDR5 SDRAM Specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4). Item 1848.99M. Committee(s): JC-42.3B Available for purchase: $369.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP) This document replaces JESD216F.01, Editorial changes to this document were approved by the TG, June 2022	JESD216F.02	Jun 2022
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office at juliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.73. Editorial changes listed in Annex, from original publication of JESD216F (December 2021). Committee(s): JC-42.4 Free download. Registration or login required.
EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES	JESD251C	May 2022
This standard specifies the eXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, which provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is primarily for use in computing, automotive, Internet Of Things (IOT), embedded systems and mobile systems, between host processing and peripheral devices. The xSPI electrical interface can deliver up to 400 MBytes per second raw data throughput. Item 1775.74. Committee(s): JC-42.4 Free download. Registration or login required.
Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs	SPD4.1.3-01	May 2022
Release No. 19.01. Item 1739.02E, Terminology update. This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROMs as used for memory module applications. Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Mobile Platform Memory Module Thermal Sensor Component Specification	MODULE4.7	May 2022
Release No. 16.This replaces Release 15 and includes the following editorial changes: 1) Replaced master/slave with controller/target 2) Checked for presence of other sensitive words 3) Added Tables and Figures in Table of Contents(Release 15, Item 1640.07) Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications	SPD4.1.4-01	May 2022
Release No. 21.01, Terminology update.This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROMs and Temperature Sensor (TS) as used for memory module applications. The designation TSE2002av refers to the family of devices specified by this document. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications	SPD4.1.6-01	May 2022
Release 26.01, Terminology update This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROM (EE) and Temperature Sensor (TS) as used for memory module applications. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
TEMPERATURE RANGE AND MEASUREMENTS FOR COMPONENTS AND MODULES	JESD402-1A	Mar 2022
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Items 1855.13, 1855.16, 1855.22, and 1855.24 Committee(s): JC-42 Free download. Registration or login required.
Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE	JESD251-1.01	Sep 2021
This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus performance than legacy SPI memory implementations. Item 1775.15. This is an editorial revision to JESD251-1, October 2018 Committee(s): JC-42.4 Free download. Registration or login required.
DDR4 SDRAM STANDARD	JESD79-4D	Jul 2021
This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78H Committee(s): JC-42.3C Available for purchase: $284.00 Add to Cart Paying JEDEC Members may login for free access.
LOW POWER DOUBLE DATA RATE 5 (LPDDR5)	JESD209-5B	Jun 2021
This document defines the LPDDR5 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5 device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3) and LPDDR4 (JESD209-4). Item 1854.99B. Committee(s): JC-42, JC-42.6 Available for purchase: $400.00 Add to Cart Paying JEDEC Members may login for free access.

Standards & Documents Search

Graphics Double Data Rate (GDDR6) SGRAM Standard

NAND Flash Interface Interoperability

STANDARD MANUFACTURERS IDENTIFICATION CODE

Graphics Double Data (GDDR4) SGRAM Standard

GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD

GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD

HIGH BANDWIDTH MEMORY (HBM3) DRAM

Secure Serial Flash Bus Transactions

Serial NOR Security Hardware Abstraction Layer

DDR5 SDRAM

SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)

EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES

Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs

Mobile Platform Memory Module Thermal Sensor Component Specification

Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications

Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications

TEMPERATURE RANGE AND MEASUREMENTS FOR COMPONENTS AND MODULES

Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE

DDR4 SDRAM STANDARD

LOW POWER DOUBLE DATA RATE 5 (LPDDR5)

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