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This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications.

Committee(s): JC-42

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This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices.

Committee(s): JC-42.6

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The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard. The purpose of this standard is to define the DDR3L specifications that supersede the DDR3 specifications as defined in JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, and DDR3L-1866 titles in JESD79-3 are to be interpreted as DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 respectively, when applying towards DDR3L definition; unless specifically stated otherwise.

Committee(s): JC-42, JC-42.3

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The purpose of this addendum is to define the DDR3U specifications that supersede the DDR3 specifications in the JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 titles in JESD79-3 are to be interpreted as DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600, respectively, when applying towards DDR3U definition; unless specifically stated otherwise. Item 1769.01

Committee(s): JC-42.3

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Committee(s): JC-42

This revision of JESD21 is substantially different from previous issues because it reflects advancement in semiconductor technology and computer design needs. A new class of memory devices, the multiport DRAM (MPDRAM) C also know as 'Video Ram' because of the most common application for the devices C is represented. A new family of SRAMs which addresses the increasing need for high speed is introduced. Additional families of devices in the SOJ and Zip packages are included. The material in this revision is organized primarily by function (ROM, EPROM, SRAM, DRAM, etc.) rather than by technology and word length. Pinouts for SIMM and DIMM are included along with presence detect schemes. A current set of terms has also been included. JESD21-C is a compilation of all memory device standards that have been developed by the JC-42 Committee and approved by the JEDEC BoD from September 1989 to present. This latest issue has changed to a loose-leaf format and comes in a three-ring binder so that new drawings can be added without requiring a new publication. Time of publication of the material is identified by release number, i.e., if marked Release 8, this item was approved and released in 1998, if marked Release 13, this item was approved and released in 2003.

Committee(s): JC-42

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This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14

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Committee(s): JC-42.3

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Version 1.31

This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4).

Committee(s): JC-42, JC-42.3

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This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices.

Committee(s): JC-42.3

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