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Title	Document #	Date
WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)	JESD229	Dec 2011
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. Committee(s): JC-42, JC-42.6 Free download. Registration or login required.
WIDE I/O 2 (WideIO2)	JESD229-2	Aug 2014
This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity. Committee(s): JC-42.6 Free download. Registration or login required.
SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)	JESD255	Mar 2024
The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
SPECIALITY DDR2-1066 SDRAM	JESD208	Nov 2007
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required.
Serial NOR Security Hardware Abstraction Layer	JESD261	Nov 2022
This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device. Committee(s): JC-42.4 Free download. Registration or login required.
SERIAL FLASH RESET SIGNALING PROTOCOL	JESD252.01	Apr 2021
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06. Committee(s): JC-42.4 Free download. Registration or login required.
Serial Flash Discoverable Parameters (SFDP)	JESD216G	Nov 2024
The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data. Committee(s): JC-42.4 Free download. Registration or login required.
Secure Serial Flash Bus Transactions Release Number: Version 1.0	JESD254	Dec 2022
This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details about the secure transactions. This ballot does not describe the SFDP revisions or the secure packet structure. Patents(): Infineon- US 10868679B1 and Micron- US 9009394B2 Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
NAND Flash Interface Interoperability	JESD230G	Oct 2024
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
Low Power Double Data Rate Interface for Non-Volatile Memory (LPDDR4X-NVM) Standard	JESD326-4	Nov 2024
This standard defines the Low Power Double Data Rate interface for Non-Volatile Memory (LPDDR4XNVM) Standard. This standard describes features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit single channel LPDDR4X-NVM device. LPDDR4X-NVM density ranges from 128Mb through 32Gb. Committee(s): JC-42, JC-42.6 Free download. Registration or login required.

Standards & Documents Search

WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)

WIDE I/O 2 (WideIO2)

SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)

SPECIALITY DDR2-1066 SDRAM

Serial NOR Security Hardware Abstraction Layer

SERIAL FLASH RESET SIGNALING PROTOCOL

Serial Flash Discoverable Parameters (SFDP)

Secure Serial Flash Bus Transactions

NAND Flash Interface Interoperability

Low Power Double Data Rate Interface for Non-Volatile Memory (LPDDR4X-NVM) Standard

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