Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
TS5111, TS5110 Serial Bus Thermal Sensor Device Standard |
JESD302-1.01 | Apr 2022 |
This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS5111 and TS5110 refers to the device specified by this document. Item 401.01E. Minor editorial changes listed in Annex A. Committee(s): JC-40.1 Free download. Registration or login required. |
||
DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1 |
JESD82-521 | Dec 2021 |
This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K Committee(s): JC-40.4 Free download. Registration or login required. |
||
DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-19A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S865 and SSTUA32D865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. This is a minor editor revision as shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
||
DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-10A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
||
DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS |
JESD82-9B.01 | Oct 2021 |
This standard provides the functional definition, ball-out configuration and package outline, signal definitions and input/output characteristics for a 28-bit 1:2 registered driver with parity suitable for use on DDR2 RDIMMs. The SSTU32865 integrates the functional equivalent of two SSTU32864 devices (as defined in JESD82-7) into a single device, thereby easing layout and board design constraints especially on high density RDIMMs such as dual rank, by four configurations. Moreover, the optional use of a parity function is provided for, permitting detection and reporting of parity errors across its 22 data inputs. JESD82-9 specifies a 160-pin Thin-profile, fine-pitch ball-grid array (TFBGA) package. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
||
DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-14A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. SSTU32S2868 denotes a single-die implementation and SSTU32D868 denotes a dual-die implementation. This is a minor editorial revision as shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
||
DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS |
JESD82-16A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
||
STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS: |
JESD82-4B.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
||
DDR5 REGISTERING CLOCK DRIVER DEFINITION (DDR5RCD01) |
JESD82-511 | Aug 2021 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD01 Device ID is DID = 0x0051. Committee(s): JC-40.4 Free download. Registration or login required. |
||
PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. 1.8 |
JESD301-1A | Aug 2021 |
Definition of PMIC5000, PMIC5010 Voltage Regulator Device for Memory Module Applications. Item 325.29C Committee(s): JC-40.1 Free download. Registration or login required. |
||
DDR4 DATA BUFFER DEFINITION (DDR4DB02) |
JESD82-32A | Aug 2019 |
This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. Item 314.11D *If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required. |
||
DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02) |
JESD82-31A | Aug 2019 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications. Any TBDs as of this document, are under discussion by the formulating committee. Item 314.08F. *If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required. |
||
DDR4 PROTOCOL CHECKS |
JEP175 | Jul 2017 |
The intended use of this document is for the validation and debug of DDR4 based designs. This document contains protocol checks, sometimes referred to as memory access rules or protocol violations. This document contains a list of checks that can be used during the verification or debug stages of development to check that accesses to a DDR4 DRAM adhere to JESD79-4B. These checks are derived from JESD79-4B. Item 31509. Committee(s): JC-40.5 Free download. Registration or login required. |
||
LRDIMM DDR3 MEMORY BUFFER (MB) |
JESD82-30 | Oct 2014 |
The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components. The Memory Buffer interface is responsible for memory requests to and from the local DIMM. LRDIMM provides a high memory bandwidth, large capacity channel solution for DDR3 main memory systems. LRDIMM uses commodity DRAMs isolated from the channel behind the Memory Buffer on the DIMM. Free download. Registration or login required. |
||
DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS |
JESD82-29A | Dec 2010 |
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications. The purpose is to provide a standard for the SSTE32882 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.3, JC-40.4 Free download. Registration or login required. |
||
FBDIMM: ADVANCED MEMORY BUFFER (AMB) |
JESD82-20A | Mar 2009 |
This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required. |
||
FULLY BUFFERED DIMM DESIGN FOR TEST, DESIGN FOR VALIDATION (DFx) |
JESD82-28A | Jul 2008 |
This FBDIMM DFx document covers Design for Test, Design for Manufacturing and Design for Validation (DFx) requirements and implementation guidelines for Fully Buffered DIMM technology. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Free download. Registration or login required. |
||
DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS |
JESD82-26 | May 2007 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. Committee(s): JC-40 Free download. Registration or login required. |
||
DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-23 | May 2007 |
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S869 and SSTUA32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. The SSTUA32S869 and SSTUA32D869 are identical in functionality to the SSTU32S869 and SSTU32D869 devices respectively but specify tighter timing characteristics and a higher application frequency of up to 410MHz. Committee(s): JC-40 Free download. Registration or login required. |
||
DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-24 | May 2007 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410MHz. Committee(s): JC-40 Free download. Registration or login required. |
||
