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2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTS:

 JESD70 Jun 1999

The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use, thus providing compatibility between devices operating between 2.3 V and 2.7 V supply voltages, as well as overvoltage tolerance with devices operating at 3.3 V, or 5 V.

Committee(s): JC-40

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BALL GRID ARRAY PINOUT FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS:

 JESD75-4 Mar 2004

This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to DSBGA-packaged 1-, 2- and 3-bit logic devices.

Committee(s): JC-40

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BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE:

 JESD75-1 Oct 2001

This standard establishes a 54 Ball Grid Array pinout for 16, 18 and 20-bit standard logic devices that are currently being produced in 48 and 56 Pin SSOP and TSSOP packages. The 54 Ball Grid Array Package is organized as a 6 x 9 array with balls on a .8mm x .8mm grid pitch.

Committee(s): JC-40

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BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16-BIT LOGIC FUNCTIONS:

 JESD75-2 Jul 2001

This standard provides a pinout standard for 16-bit wide logic devices offered in a 56-ball areagrid array package to provide for uniformity, multiplicity of sources, elimination of confusion,ease of device specification, and ease of use.

Committee(s): JC-40

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BALL GRID ARRAY PINOUTS STANDARDIZED FOR 32-BIT LOGIC FUNCTIONS:

 JESD75 Nov 1999

The purpose of this standard is to provide a pinout standard for dual-die 32-bit logic devices offered in a 96- and 144-ball grid array package for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease use. This standard defines device output for 32-bit wide buffer, driver and transceiver functions. This pinout specifically applies to the conversion of DIP-packaged 16-bit logic devices to LFBGA-packaged dual-die 32-bit logic devices.

Committee(s): JC-40

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BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS:

 JESD75-3 Jul 2001

This standard provides a pinout standard for 8-bit logic devices offered in a 20-ball area gridarray package to provide for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS:

 JESD11 Dec 1984

This standard indicates the procedures used to convert existing DIP and flat packages for digital parts (SSI & MSI) to chip carrier packages.

Committee(s): JC-40.2

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DDR4 DATA BUFFER DEFINITION (DDR4DB02)

 JESD82-32A Aug 2019

This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. Item 314.11D

*If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-40.4

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DDR4 PROTOCOL CHECKS

 JEP175 Jul 2017

The intended use of this document is for the validation and debug of DDR4 based designs. This document contains protocol checks, sometimes referred to as memory access rules or protocol violations. This document contains a list of checks that can be used during the verification or debug stages of development to check that accesses to a DDR4 DRAM adhere to JESD79-4B. These checks are derived from JESD79-4B. Item 31509.

Committee(s): JC-40.5

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DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)

 JESD82-31A.01 Jan 2023

Terminology update.

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-40.4

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DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1

 JESD82-521 Dec 2021

This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K

Committee(s): JC-40.4

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DDR5 Clock Driver Definition (DDR5CKD01)

Release Number: Version 1.1 		JESD82-531A.01 Feb 2024

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5,
3= Clock Driver, 1= rev 01)

Committee(s): JC-40, JC-40.4

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DDR5 REGISTERING CLOCK DRIVER DEFINITION (DDR5RCD01)

 JESD82-511 Aug 2021

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD01 Device ID is DID = 0x0051.

Committee(s): JC-40.4

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DDR5 Registering Clock Driver Definition (DDR5RCD02)

Release Number: Rev. 1.00 		JESD82-512 Feb 2023

This standard defines specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD02 Device ID is DID = 0x0052.

Committee(s): JC-40, JC-40.4

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DDR5 Registering Clock Driver Definition (DDR5RCD03)

Release Number: 1.00 		JESD82-513 Feb 2023

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD03 Device ID is DID = 0x0053.

Committee(s): JC-40, JC-40.5

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DDR5 Registering Clock Driver Definition (DDR5RCD04)

 JESD82-514.01 Jun 2024

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054.

Committee(s): JC-40, JC-40.4

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DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS:

 JESD82 Jul 2000

This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as refined in revision C of JEDEC Standard 21-C (JESD21-C). JESD82 was also written to meet the future performance requirements of Registered DIMMs for DDR300 and DDR333.

Committee(s): JC-40

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DEFINITION OF CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

 JESD82-11 Sep 2004

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CU878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CU878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.3

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DEFINITION OF CVF857 PLL CLOCK DRIVER FOR REGISTERED PC1600, PC2100, PC2700, AND PC3200 DIMM APPLICATIONS:

 JESD82-1A May 2004

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CV857 PLL clock device for registered PC1600, PC2100, PC2700 and PC3200 DIMM applications. The purpose is to provide a standard for a CV857 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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DEFINITION OF SKEW SPECIFICATIONS FOR STANDARD LOGIC DEVICES:

 JESD65B Sep 2003

This standard defines skew specifications and skew testing for standard logic devices. The purpose is to provide a standard for specifications to achieve uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users.

Committee(s): JC-40

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DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

 JESD82-9B.01 Oct 2021

This standard provides the functional definition, ball-out configuration and package outline, signal definitions and input/output characteristics for a 28-bit 1:2 registered driver with parity suitable for use on DDR2 RDIMMs. The SSTU32865 integrates the functional equivalent of two SSTU32864 devices (as defined in JESD82-7) into a single device, thereby easing layout and board design constraints especially on high density RDIMMs such as dual rank, by four configurations. Moreover, the optional use of a parity function is provided for, permitting detection and reporting of parity errors across its 22 data inputs. JESD82-9 specifies a 160-pin Thin-profile, fine-pitch ball-grid array (TFBGA) package. This is a minor editorial revision as shown in Annex A of the document.

Committee(s): JC-40, JC-40.4

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DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

 JESD82-29A.01 Jan 2023

Terminology update.
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications.

The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.3, JC-40.4

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DEFINITION OF THE SSTU32864 1.8 V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS:

 JESD82-7A.01 Feb 2023

Terminology update.

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32864 configurable registered buffer for DDR2 RDIMM applications.

Committee(s): JC-40, JC-40.4

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DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

 JESD82-10A.01 Oct 2021

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document.

Committee(s): JC-40, JC-40.4

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DEFINITION OF THE SSTU32S869 AND SSTU32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

 JESD82-12A.01 Feb 2023

Terminology update.
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32S869 and SSTU32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.

Committee(s): JC-40

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DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS

 JESD82-16A.01 Oct 2021

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document.

Committee(s): JC-40, JC-40.3

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DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

 JESD82-19A.01 Oct 2021

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S865 and SSTUA32D865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. This is a minor editor revision as shown in Annex A of the document.

Committee(s): JC-40

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DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 REGISTERED BUFFER WITH PARITY FOR 2R X 4 DDR2 RDIMM APPLICATIONS

 JESD82-17.01 Feb 2023

(Terminology update.)  

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for DDR2 RDIMM applications.

Committee(s): JC-40, JC-40.3

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DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

 JESD82-23.01 Jan 2023

Terminology update.  
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S869 and SSTUA32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. The SSTUA32S869 and SSTUA32D869 are identical in functionality to the SSTU32S869 and SSTU32D869 devices respectively but specify tighter timing characteristics and a higher application frequency of up to 410MHz.

Committee(s): JC-40

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DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

 JESD82-24.01 Jan 2023

 Terminology update.

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or similar high density DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410 MHz.

Committee(s): JC-40

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DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

 JESD82-25.01 Jan 2023

Terminology update.
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications.

Committee(s): JC-40

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DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

 JESD82-14A.01 Oct 2021

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. SSTU32S2868 denotes a single-die implementation and SSTU32D868 denotes a dual-die implementation. This is a minor editorial revision as shown in Annex A of the document.

Committee(s): JC-40

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DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

 JESD82-26.01 Jan 2023

Terminology update.  
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUB32868 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications

 JESD82-27.01 Mar 2023

Terminology update.  

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.

Committee(s): JC-40

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DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS:

 JESD82-3B.01 Jan 2023

Terminology update.
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTVN16857 14-bit SSTL_2 registered buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM applications.

Committee(s): JC-40, JC-40.3

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DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS:

 JESD82-6A.01 Jan 2023

Terminology update.

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the 32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications.

Committee(s): JC-40

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DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS

 JESD82-13A.01 Mar 2023

Terminology update.   

Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications

Committee(s): JC-40

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DESCRIPTION OF 1.8 V CMOS LOGIC DEVICES:

 JESD76 Apr 2000

This standard continues the voltage specification migration to the next level beyond the 2.5 V specification already established in JESD80. In this standard, the input and output conditions are described for CMOS Logic products in a 1.8 V (Normal Range) application.

Committee(s): JC-40.1

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DESCRIPTION OF 5 V BUS SWITCH WITH TTL-COMPATIBLE CONTROL INPUTS:

 JESD73 Jun 1999

This standard covers specifications for a family of 5 V NMOS FET bus switch devices with 5 V TTL compatible control inputs. Not included in this document are device-specific parameters and performance levels that the vendor must also apply for full device description.

Committee(s): JC-40

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DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS:

 JESD2 Dec 1982

This standard provides a chip carrier format for digital devices by defining pin functions and locations for 20, 38, 44, 52, and 68-terminal devices.

Committee(s): JC-40.1

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FBDIMM: ARCHITECTURE AND PROTOCOL

 JESD206.01 Feb 2023

Terminology update. 
This standard includes four chapters of the FBD Channel Specification (cover) Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chapter 4), and Reliability, Availability, and Serviceability (RAS) (Chapter 5).

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40

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FBDIMM: ADVANCED MEMORY BUFFER (AMB)

 JESD82-20A.01 Jan 2023

This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40

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Fully Buffered DIMM Design for Test, Design for Validation (DFx)

 JESD82-28A.01 Mar 2023

Terminology update.  

This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40, JC-40.5

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INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES

 JESD82-22.01 Feb 2023

Terminology update.
This device is a one-chip spectrum analyzer that operates in the frequency range from 1 to 2 GHz.It requires no external components except some filtering of the voltage supply (one inductor, one bypass capacitor).
The frequency of the VCO is adjusted by an internal DAC. No PLL loop is used to lock the VCO to a reference frequency. A counter is used to determine the VCO frequency.

Committee(s): JC-40, JC-40.4

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JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)

 JESD319 Sep 2024

This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC).

Committee(s): JC-40

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JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®)

 JESD325 Sep 2024

This standard provides a reference specification for systems and device management capabilities found in CXL memory devices. It is intended to target, but may not be limited to, CXL memory FRUs that are based on PCIe Gen 5 and compliant to the CXL 2.0 Specification or later.

Committee(s): JC-40, JC-45

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LATCH-UP IN CMOS INTEGRATED CIRCUITS - SUPERSEDED BY JESD78, February 1999

Status: RescindedFebruary 1999 		JESD17 Aug 1988

This document is no longer available via the JEDEC website to obtain a copy please contact JEDEC.

Committee(s): JC-40.2

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LRDIMM DDR3 MEMORY BUFFER (MB)

 JESD82-30.01 Jan 2023

Terminology update.

The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components.

Committee(s): JC-40, JC-40.4

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PMIC5000/PMIC5010 Power Management IC Standard

 JESD301-1A.03 Feb 2025

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

This is a minor update to correct the document name, and also remove the extraneous hard return in the middle of the description between “as” and “used”.

Committee(s): JC-40.1

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PMIC5020 Power Management IC Standard

Release Number: Version 1.1 		JESD301-4A Mar 2025

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document.

 

The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.1

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PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03

 JESD301-2 Oct 2022

This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5100 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5100 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 336.01C

Committee(s): JC-40.1

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PMIC5120 Power Management IC Standard

Release Number: Version 1.0 		JESD301-6 Feb 2025

This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5120 refers to the device specified by this document.

The purpose is to provide a standard for the PMIC5120 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Unless otherwise noted in the document, any illegal operation is not allowed and device operation is not guaranteed.

Committee(s): JC-40, JC-40.1

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PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONS:

 JESD75-6 Mar 2006

This standard defines device pinouts for 14-, 16-, 20-, and 24-lead logic functions. This pinout standard specifically applies to the conversion of DIP-packaged logic devices to PSO-N/PQFN packages logic devices

The purpose of this standard is to provide a pinout standard for 14-, 16-, 20-, and 24-lead logic devices offered in 14-, 16-, 20-, and 24-lead PSO-N/PQFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use

Committee(s): JC-40, JC-40.1

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RECOMMENDED CHARACTERIZATION OF MOS SHIFT REGISTERS:

 JEB19 Jan 1972

This recommendation applies to MOS Shift Registers. Definitions are given for P-channel registers but are applicable to all CMOS and N-channel with changes in power supply notation.

Committee(s): JC-40

SON/QFN PACKAGE PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS

 JESD75-5 Jul 2004

This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and 3-bit logic devices.

The purpose of this document is to provide a pinout standard for 1-, 2- and 3-bit logic devices offered in 5-, 6- or 8-land SON/QFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.1

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SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD

Release Number: Version 1.5.1 		JESD300-5B.01 May 2023

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard.

Committee(s): JC-40.1

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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION):

 JESD76-2 Jun 2001

This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (normal range) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION):

 JESD76-1 Jun 2001

This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (nominal) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES:

 JESD76-3 Aug 2001

This standard continues the voltage specification migration to the next level beyond the 1.8 V specification already established. The purpose is to provide a standard for 1.5 V nominal supply voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.1

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STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES:

 JESD36 Jun 1996

This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses.

Committee(s): JC-40

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