Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
PMIC5120 Power Management IC StandardRelease Number: Version 1.0 |
JESD301-6 | Feb 2025 |
This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5120 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5120 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Unless otherwise noted in the document, any illegal operation is not allowed and device operation is not guaranteed. Free download. Registration or login required. |
||
PMIC5000/PMIC5010 Power Management IC Standard |
JESD301-1A.03 | Feb 2025 |
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor update to correct the document name, and also remove the extraneous hard return in the middle of the description between “as” and “used”. Committee(s): JC-40.1 Free download. Registration or login required. |
||
JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®) |
JESD319 | Sep 2024 |
This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC). Committee(s): JC-40 Free download. Registration or login required. |
||
JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®) |
JESD325 | Sep 2024 |
This standard provides a reference specification for systems and device management capabilities found in CXL memory devices. It is intended to target, but may not be limited to, CXL memory FRUs that are based on PCIe Gen 5 and compliant to the CXL 2.0 Specification or later. Free download. Registration or login required. |
||
DDR5 Registering Clock Driver Definition (DDR5RCD04) |
JESD82-514.01 | Jun 2024 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054. Free download. Registration or login required. |
||
