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Title	Document #	Date
JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)	JESD319	Sep 2024
This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC). Committee(s): JC-40 Free download. Registration or login required.
JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®)	JESD325	Sep 2024
This standard provides a reference specification for systems and device management capabilities found in CXL memory devices. It is intended to target, but may not be limited to, CXL memory FRUs that are based on PCIe Gen 5 and compliant to the CXL 2.0 Specification or later. Committee(s): JC-40, JC-45 Free download. Registration or login required.
DDR5 Registering Clock Driver Definition (DDR5RCD04)	JESD82-514.01	Jun 2024
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
PMIC5020 Power Management IC Standard Release Number: Version 1.0.1	JESD301-4	Apr 2024
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.1 Free download. Registration or login required.
DDR5 Clock Driver Definition (DDR5CKD01) Release Number: Version 1.1	JESD82-531A.01	Feb 2024
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5, 3= Clock Driver, 1= rev 01) Committee(s): JC-40, JC-40.4 Free download. Registration or login required.

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