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Title	Document #	Date
TS511X, TS521X Serial Bus Thermal Sensor Device Standard	JESD302-1A	Aug 2023
This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document. Committee(s): JC-40.1 Free download. Registration or login required.
SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD Release Number: Version 1.5.1	JESD300-5B.01	May 2023
This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard. Committee(s): JC-40.1 Free download. Registration or login required.
PMIC50x0 Power Management IC Standard	JESD301-1A.02 Rev. 1.8.5	Apr 2023
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40.1 Free download. Registration or login required.
Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications	JESD82-27.01	Mar 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. Committee(s): JC-40 Free download. Registration or login required.
Fully Buffered DIMM Design for Test, Design for Validation (DFx)	JESD82-28A.01	Mar 2023
Terminology update. This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40, JC-40.5 Free download. Registration or login required.

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