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FBDIMM: ARCHITECTURE AND PROTOCOL

 JESD206.01 Feb 2023

Terminology update. 
This standard includes four chapters of the FBD Channel Specification (cover) Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chapter 4), and Reliability, Availability, and Serviceability (RAS) (Chapter 5).

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40

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FBDIMM: ADVANCED MEMORY BUFFER (AMB)

 JESD82-20A.01 Jan 2023

This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40

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Fully Buffered DIMM Design for Test, Design for Validation (DFx)

 JESD82-28A.01 Mar 2023

Terminology update.  

This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40, JC-40.5

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INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES

 JESD82-22.01 Feb 2023

Terminology update.
This device is a one-chip spectrum analyzer that operates in the frequency range from 1 to 2 GHz.It requires no external components except some filtering of the voltage supply (one inductor, one bypass capacitor).
The frequency of the VCO is adjusted by an internal DAC. No PLL loop is used to lock the VCO to a reference frequency. A counter is used to determine the VCO frequency.

Committee(s): JC-40, JC-40.4

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JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)

 JESD319 Sep 2024

This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC).

Committee(s): JC-40

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JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®)

 JESD325 Sep 2024

This standard provides a reference specification for systems and device management capabilities found in CXL memory devices. It is intended to target, but may not be limited to, CXL memory FRUs that are based on PCIe Gen 5 and compliant to the CXL 2.0 Specification or later.

Committee(s): JC-40, JC-45

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LATCH-UP IN CMOS INTEGRATED CIRCUITS - SUPERSEDED BY JESD78, February 1999

Status: RescindedFebruary 1999 		JESD17 Aug 1988

This document is no longer available via the JEDEC website to obtain a copy please contact JEDEC.

Committee(s): JC-40.2

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LRDIMM DDR3 MEMORY BUFFER (MB)

 JESD82-30.01 Jan 2023

Terminology update.

The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components.

Committee(s): JC-40, JC-40.4

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PMIC5020 Power Management IC Standard

Release Number: Version 1.0.1 		JESD301-4 Apr 2024

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document.

The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.1

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PMIC50x0 Power Management IC Standard

 JESD301-1A.02 Rev. 1.8.5 Apr 2023

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as

used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40.1

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PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03

 JESD301-2 Oct 2022

This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5100 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5100 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 336.01C

Committee(s): JC-40.1

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PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONS:

 JESD75-6 Mar 2006

This standard defines device pinouts for 14-, 16-, 20-, and 24-lead logic functions. This pinout standard specifically applies to the conversion of DIP-packaged logic devices to PSO-N/PQFN packages logic devices

The purpose of this standard is to provide a pinout standard for 14-, 16-, 20-, and 24-lead logic devices offered in 14-, 16-, 20-, and 24-lead PSO-N/PQFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use

Committee(s): JC-40, JC-40.1

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RECOMMENDED CHARACTERIZATION OF MOS SHIFT REGISTERS:

 JEB19 Jan 1972

This recommendation applies to MOS Shift Registers. Definitions are given for P-channel registers but are applicable to all CMOS and N-channel with changes in power supply notation.

Committee(s): JC-40

SON/QFN PACKAGE PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS

 JESD75-5 Jul 2004

This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and 3-bit logic devices.

The purpose of this document is to provide a pinout standard for 1-, 2- and 3-bit logic devices offered in 5-, 6- or 8-land SON/QFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.1

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SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD

Release Number: Version 1.5.1 		JESD300-5B.01 May 2023

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard.

Committee(s): JC-40.1

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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION):

 JESD76-2 Jun 2001

This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (normal range) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION):

 JESD76-1 Jun 2001

This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (nominal) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES:

 JESD76-3 Aug 2001

This standard continues the voltage specification migration to the next level beyond the 1.8 V specification already established. The purpose is to provide a standard for 1.5 V nominal supply voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.1

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STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES:

 JESD36 Jun 1996

This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVE FOR REGISTERED DDR2 DIMM APPLICATION

 JESD82-8.01 Feb 2004

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a íCU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a íCU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This document includes minor editorial changes as noted in Annex A, page 16.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

 JESD82-21 Jan 2007

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

 JESD82-15 Nov 2005

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CUA878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS

 JESD82-18A Jan 2007

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS:

 JESD82-4B.01 Oct 2021

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS:

 JESD64-A Oct 2000

The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification provides for compatibility between devices operating between either the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 V supply voltages, as well as over-voltage tolerance with devices operating at 3.6 V.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES:

 JESD80 Nov 1999

The purpose of this standard is to provide a standard for 2.5 V nominal supply-voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This standard defines dc interface parameters and test loading for CMOS digital logic family based on 2.5 V (nominal) power supply levels at 2.5 V input tolerance.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS:

 JESD73-2 Aug 2001

This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices with integrated charge pumps. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this standard is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES:

 JESD73-1 Aug 2001

This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this document is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCH:

 JESD73-3 Nov 2001

This standard provides a set of uniform data sheet parameters for the description of a single 10-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay.

Committee(s): JC-40, JC-40.2

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STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH:

 JESD73-4 Nov 2001

This standard provides a set of uniform data sheet parameters for the description of a dual 5-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay.

Committee(s): JC-40, JC-40.2

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STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES:

 JESD54 Feb 1996

The purpose is to provide a standard of BiCMOS Logic series specifications to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:

Release Number: Pt 2 		JESD20 Jan 1990

This standard describes electrical parameters for this class of CMOS devices.

Committee(s): JC-40.2

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STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:

Release Number: Pt 1 		JESD20 Jan 1990

This standard describes electrical parameters for this class of CMOS devices.

Committee(s): JC-40.2

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STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES:

 JESD7-A Aug 1986

This standard provides uniformity, multiplicity of sources, eliminate confusion, and ease of device specification and design by users for HC, and HCT CMOS devices. This standard specifies electrical parameters. It also includes appendices listing part numbers.

Committee(s): JC-40.2

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STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:

 JESD82-2 Jul 2001

This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION

 JESD82-5 Jul 2002

This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC:

 JESD18-A Jan 1993

The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. The standard covers specifications for description of '54/74FCTXXXX' series fast CMOS TTL compatible devices.

Committee(s): JC-40.2

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STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES:

 JESD52 Nov 1995

This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES:

 JESD55 May 1996

The purpose is to provide a standard of BiCMOS Logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users.

Committee(s): JC-40

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STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS DEVICES:

 JESD13-B May 1980

This standard provides for uniformity, multiplicity of sources, elimination of confusion, and ease of device specifications and system design by users. It gives electrical levels and timing diagrams for B Series CMOS devices.

Committee(s): JC-40.2

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