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Title Document # Date

FBDIMM: ADVANCED MEMORY BUFFER (AMB)

 JESD82-20A.01 Jan 2023

This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40

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INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES

 JESD82-22.01 Feb 2023

Terminology update.
This device is a one-chip spectrum analyzer that operates in the frequency range from 1 to 2 GHz.It requires no external components except some filtering of the voltage supply (one inductor, one bypass capacitor).
The frequency of the VCO is adjusted by an internal DAC. No PLL loop is used to lock the VCO to a reference frequency. A counter is used to determine the VCO frequency.

Committee(s): JC-40, JC-40.4

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BALL GRID ARRAY PINOUTS STANDARDIZED FOR 32-BIT LOGIC FUNCTIONS:

 JESD75 Nov 1999

The purpose of this standard is to provide a pinout standard for dual-die 32-bit logic devices offered in a 96- and 144-ball grid array package for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease use. This standard defines device output for 32-bit wide buffer, driver and transceiver functions. This pinout specifically applies to the conversion of DIP-packaged 16-bit logic devices to LFBGA-packaged dual-die 32-bit logic devices.

Committee(s): JC-40

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DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

 JESD82-29A.01 Jan 2023

Terminology update.
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications.

The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.3, JC-40.4

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LATCH-UP IN CMOS INTEGRATED CIRCUITS - SUPERSEDED BY JESD78, February 1999

Status: RescindedFebruary 1999 		JESD17 Aug 1988

This document is no longer available via the JEDEC website to obtain a copy please contact JEDEC.

Committee(s): JC-40.2

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FBDIMM: ARCHITECTURE AND PROTOCOL

 JESD206.01 Feb 2023

Terminology update. 
This standard includes four chapters of the FBD Channel Specification (cover) Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chapter 4), and Reliability, Availability, and Serviceability (RAS) (Chapter 5).

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40

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LRDIMM DDR3 MEMORY BUFFER (MB)

 JESD82-30.01 Jan 2023

Terminology update.

The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components.

Committee(s): JC-40, JC-40.4

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DDR4 DATA BUFFER DEFINITION (DDR4DB02)

 JESD82-32A Aug 2019

This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. Item 314.11D

*If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-40.4

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DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)

 JESD82-31A.01 Jan 2023

Terminology update.

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-40.4

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DDR4 PROTOCOL CHECKS

 JEP175 Jul 2017

The intended use of this document is for the validation and debug of DDR4 based designs. This document contains protocol checks, sometimes referred to as memory access rules or protocol violations. This document contains a list of checks that can be used during the verification or debug stages of development to check that accesses to a DDR4 DRAM adhere to JESD79-4B. These checks are derived from JESD79-4B. Item 31509.

Committee(s): JC-40.5

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SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD

Release Number: Version 1.5.1 		JESD300-5B.01 May 2023

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard.

Committee(s): JC-40.1

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PMIC50x0 Power Management IC Standard

 JESD301-1A.02 Rev. 1.8.5 Apr 2023

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as

used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40.1

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DDR5 REGISTERING CLOCK DRIVER DEFINITION (DDR5RCD01)

 JESD82-511 Aug 2021

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD01 Device ID is DID = 0x0051.

Committee(s): JC-40.4

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TS511X, TS521X Serial Bus Thermal Sensor Device Standard

 JESD302-1A Aug 2023

This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document.

Committee(s): JC-40.1

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DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1

 JESD82-521 Dec 2021

This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K

Committee(s): JC-40.4

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PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03

 JESD301-2 Oct 2022

This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5100 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5100 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 336.01C

Committee(s): JC-40.1

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DDR5 Registering Clock Driver Definition (DDR5RCD02)

Release Number: Rev. 1.00 		JESD82-512 Feb 2023

This standard defines specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD02 Device ID is DID = 0x0052.

Committee(s): JC-40, JC-40.4

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DDR5 Registering Clock Driver Definition (DDR5RCD03)

Release Number: 1.00 		JESD82-513 Feb 2023

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD03 Device ID is DID = 0x0053.

Committee(s): JC-40, JC-40.5

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DDR5 Clock Driver Definition (DDR5CKD01)

Release Number: Version 1.1 		JESD82-531A.01 Feb 2024

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5,
3= Clock Driver, 1= rev 01)

Committee(s): JC-40, JC-40.4

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PMIC5020 Power Management IC Standard

Release Number: Version 1.0.1 		JESD301-4 Apr 2024

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document.

The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.1

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