Standards & Documents Search

Displaying 41 - 50 of 83 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
Fully Buffered DIMM Design for Test, Design for Validation (DFx)	JESD82-28A.01	Mar 2023
Terminology update. This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40, JC-40.5 Free download. Registration or login required.
FBDIMM: ADVANCED MEMORY BUFFER (AMB)	JESD82-20A.01	Jan 2023
This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
FBDIMM: ARCHITECTURE AND PROTOCOL	JESD206.01	Feb 2023
Terminology update. This standard includes four chapters of the FBD Channel Specification (cover) Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chapter 4), and Reliability, Availability, and Serviceability (RAS) (Chapter 5). Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS:	JESD2	Dec 1982
This standard provides a chip carrier format for digital devices by defining pin functions and locations for 20, 38, 44, 52, and 68-terminal devices. Committee(s): JC-40.1 Free download. Registration or login required.
DESCRIPTION OF 5 V BUS SWITCH WITH TTL-COMPATIBLE CONTROL INPUTS:	JESD73	Jun 1999
This standard covers specifications for a family of 5 V NMOS FET bus switch devices with 5 V TTL compatible control inputs. Not included in this document are device-specific parameters and performance levels that the vendor must also apply for full device description. Committee(s): JC-40 Free download. Registration or login required.
DESCRIPTION OF 1.8 V CMOS LOGIC DEVICES:	JESD76	Apr 2000
This standard continues the voltage specification migration to the next level beyond the 2.5 V specification already established in JESD80. In this standard, the input and output conditions are described for CMOS Logic products in a 1.8 V (Normal Range) application. Committee(s): JC-40.1 Free download. Registration or login required.
DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS	JESD82-13A.01	Mar 2023
Terminology update. Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS:	JESD82-6A.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the 32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS:	JESD82-3B.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTVN16857 14-bit SSTL_2 registered buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM applications. Committee(s): JC-40, JC-40.3 Free download. Registration or login required.
Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications	JESD82-27.01	Mar 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. Committee(s): JC-40 Free download. Registration or login required.

Standards & Documents Search

Fully Buffered DIMM Design for Test, Design for Validation (DFx)

FBDIMM: ADVANCED MEMORY BUFFER (AMB)

FBDIMM: ARCHITECTURE AND PROTOCOL

DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS:

DESCRIPTION OF 5 V BUS SWITCH WITH TTL-COMPATIBLE CONTROL INPUTS:

DESCRIPTION OF 1.8 V CMOS LOGIC DEVICES:

DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS

DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS:

DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS:

Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications

Pages

Search by Keyword or Document Number

Filter by committees:

Filter by document type:

Filter by keywords: