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Title	Document #	Date
RECOMMENDED CHARACTERIZATION OF MOS SHIFT REGISTERS:	JEB19	Jan 1972
This recommendation applies to MOS Shift Registers. Definitions are given for P-channel registers but are applicable to all CMOS and N-channel with changes in power supply notation. Committee(s): JC-40
PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONS:	JESD75-6	Mar 2006
This standard defines device pinouts for 14-, 16-, 20-, and 24-lead logic functions. This pinout standard specifically applies to the conversion of DIP-packaged logic devices to PSO-N/PQFN packages logic devices The purpose of this standard is to provide a pinout standard for 14-, 16-, 20-, and 24-lead logic devices offered in 14-, 16-, 20-, and 24-lead PSO-N/PQFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use Committee(s): JC-40, JC-40.1 Free download. Registration or login required.
PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03	JESD301-2	Oct 2022
This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5100 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5100 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 336.01C Committee(s): JC-40.1 Free download. Registration or login required.
PMIC50x0 Power Management IC Standard	JESD301-1A.02 Rev. 1.8.5	Apr 2023
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40.1 Free download. Registration or login required.
PMIC5020 Power Management IC Standard Release Number: Version 1.0.1	JESD301-4	Apr 2024
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.1 Free download. Registration or login required.
LRDIMM DDR3 MEMORY BUFFER (MB)	JESD82-30.01	Jan 2023
Terminology update. The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
LATCH-UP IN CMOS INTEGRATED CIRCUITS - SUPERSEDED BY JESD78, February 1999 Status: RescindedFebruary 1999	JESD17	Aug 1988
This document is no longer available via the JEDEC website to obtain a copy please contact JEDEC. Committee(s): JC-40.2 Free download. Registration or login required.
JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®)	JESD325	Sep 2024
This standard provides a reference specification for systems and device management capabilities found in CXL memory devices. It is intended to target, but may not be limited to, CXL memory FRUs that are based on PCIe Gen 5 and compliant to the CXL 2.0 Specification or later. Committee(s): JC-40, JC-45 Free download. Registration or login required.
JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)	JESD319	Sep 2024
This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC). Committee(s): JC-40 Free download. Registration or login required.
INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES	JESD82-22.01	Feb 2023
Terminology update. This device is a one-chip spectrum analyzer that operates in the frequency range from 1 to 2 GHz.It requires no external components except some filtering of the voltage supply (one inductor, one bypass capacitor). The frequency of the VCO is adjusted by an internal DAC. No PLL loop is used to lock the VCO to a reference frequency. A counter is used to determine the VCO frequency. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.

Standards & Documents Search

RECOMMENDED CHARACTERIZATION OF MOS SHIFT REGISTERS:

PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONS:

PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03

PMIC50x0 Power Management IC Standard

PMIC5020 Power Management IC Standard

LRDIMM DDR3 MEMORY BUFFER (MB)

LATCH-UP IN CMOS INTEGRATED CIRCUITS - SUPERSEDED BY JESD78, February 1999

JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®)

JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)

INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES

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