Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
TERMINOLOGY AND METHODS OF MEASUREMENT FOR BISTABLE SEMICONDUCTOR MICROCIRCUITS: |
JEB15 | Jan 1969 |
This bulletin explains the terminology and methods of measurement for bistable semiconductor microcircuits. It is also intended to be used with the EIA Registration Data Format for semiconductor integrated bistable logic circuits. Committee(s): JC-40 |
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RECOMMENDED CHARACTERIZATION OF MOS SHIFT REGISTERS: |
JEB19 | Jan 1972 |
This recommendation applies to MOS Shift Registers. Definitions are given for P-channel registers but are applicable to all CMOS and N-channel with changes in power supply notation. Committee(s): JC-40 |
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STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS DEVICES: |
JESD13-B | May 1980 |
This standard provides for uniformity, multiplicity of sources, elimination of confusion, and ease of device specifications and system design by users. It gives electrical levels and timing diagrams for B Series CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS: |
JESD2 | Dec 1982 |
This standard provides a chip carrier format for digital devices by defining pin functions and locations for 20, 38, 44, 52, and 68-terminal devices. Committee(s): JC-40.1 Free download. Registration or login required. |
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CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS: |
JESD11 | Dec 1984 |
This standard indicates the procedures used to convert existing DIP and flat packages for digital parts (SSI & MSI) to chip carrier packages. Committee(s): JC-40.2 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES: |
JESD7-A | Aug 1986 |
This standard provides uniformity, multiplicity of sources, eliminate confusion, and ease of device specification and design by users for HC, and HCT CMOS devices. This standard specifies electrical parameters. It also includes appendices listing part numbers. Committee(s): JC-40.2 Free download. Registration or login required. |
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LATCH-UP IN CMOS INTEGRATED CIRCUITS - SUPERSEDED BY JESD78, February 1999Status: RescindedFebruary 1999 |
JESD17 | Aug 1988 |
This document is no longer available via the JEDEC website to obtain a copy please contact JEDEC. Committee(s): JC-40.2 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:Release Number: Pt 1 |
JESD20 | Jan 1990 |
This standard describes electrical parameters for this class of CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:Release Number: Pt 2 |
JESD20 | Jan 1990 |
This standard describes electrical parameters for this class of CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC: |
JESD18-A | Jan 1993 |
The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. The standard covers specifications for description of '54/74FCTXXXX' series fast CMOS TTL compatible devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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